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Altera_Forum
Honored Contributor I
1,231 Views

yocto linux and dtb with tse

Hi community, 

 

I try to generate a dtb-file to get linux communicating with the tse-interfaces. 

I know how to generate a dtb file (http://www.rocketboards.org/foswiki/documentation/gsrd141devicetreegenerator

And as much as possible I followed this tutorial: http://rocketboards.org/foswiki/projects/alterasoctriplespeedethernetdesignexample 

I have Quartus 14.1 installed instead of the used version 14.0. 

 

So I can not use the dtb file. 

Where do I get the information about what is needed to write additional into the xml files for recognising the tse_interfaces. 

 

My Linux Yocto/Angstrom is booting, the driver "altera_tse" is loaded. 

But on boot-up following error message shows up: 

altera_tse c0010000.ethernet: resource s1 not defined 

(where c0010000 is the base address of the tse_interface) 

 

What do I need to add to the xml-files for full recognising the tse_interfaces? 

If it wouldn't be the tse-ip-cores? Where do I get the same information? I can't allways ask in this forum... 

Thanks in advance, 

 

fabian
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4 Replies
Altera_Forum
Honored Contributor I
57 Views

You may want to look at Rocketboards rfi traffic or join and post there. I think I saw some traffic on the tse.

Altera_Forum
Honored Contributor I
57 Views

thanks for your answer. 

 

I tried to join the email list of rocketboards, but didn't get any answer or possibility to write a email... 

 

It seems that the problem is not with the dtb file. 

Instead by the quartus compilation. 

If I compile my design under windows it succeeds but doesn't program any more. 

If I compile under Linux the step "Analysis & Synthesis" keeps standing at 46% and I have to quit quartus, because it doesn't react anymore. 

 

So I am still on this problem. And it seems another 50 people too (who viewed this thread, but didn't answer)
Altera_Forum
Honored Contributor I
57 Views

Hi again, 

 

updating this thread for other people with the same problem: 

 

The compilation standing at 46% was caused by windows to linux portation. Linux stopped because of the "\n" in some scripts. 

Setting up a new project under linux and copying only the needed files helps for this problem. 

 

Another problem was that the fpga reset pin was the complete time high or low (didn't look for the signal), so there was no access... 

If you "hardcode" the reset signal in the vhdl design to 1 (high), I can access the fpga. 

 

Now I am still at the problem of the TSE recognising by linux boot... 

 

I get the following messages: 

mdio_bus altera_tse-0: cannot get PHY at address 0 

mdio_bus altera_tse-0: cannot get PHY at address 1 

altera_tse ff200000.ethernet (unregistered net_device): MDIO bus altera_tse-0: created 

altera_tse ff200000.ethernet: Altera TSE MAC version 15.0 at 0xff200000 irq 72/73 

altera_tse ff200000.ethernet eth0: Could not find the PHY 

altera_tse ff200000.ethernet eth0: Cannot attach to PHY (error: -19) 

altera_tse ff200000.ethernet (unregistered net_device): MDIO bus altera_tse-0: removed 

altera_tse ff201000.ethernet: Altera TSE MAC version 15.0 at 0xff201000 irq 75/76 

altera_tse ff201000.ethernet eth0: Could not find the PHY 

altera_tse ff201000.ethernet eth0: Cannot attach to PHY (error: -19) 

 

But either in the sources nor in the www I can find anything about error -19 

After booting the network is not listed under "ip addr", too. 

 

Where can I search for the problem? 

Where do I get more information? 

Where is my problem? 

How can I check if the bridge between hps and fpga is set up correct?
Altera_Forum
Honored Contributor I
57 Views

Hi all, 

 

I have the same problem, have you any progress? 

Did you find solutions of this problem? 

 

Regards 

 

 

--- Quote Start ---  

Hi again, 

 

updating this thread for other people with the same problem: 

 

The compilation standing at 46% was caused by windows to linux portation. Linux stopped because of the "\n" in some scripts. 

Setting up a new project under linux and copying only the needed files helps for this problem. 

 

Another problem was that the fpga reset pin was the complete time high or low (didn't look for the signal), so there was no access... 

If you "hardcode" the reset signal in the vhdl design to 1 (high), I can access the fpga. 

 

Now I am still at the problem of the TSE recognising by linux boot... 

 

I get the following messages: 

mdio_bus altera_tse-0: cannot get PHY at address 0 

mdio_bus altera_tse-0: cannot get PHY at address 1 

altera_tse ff200000.ethernet (unregistered net_device): MDIO bus altera_tse-0: created 

altera_tse ff200000.ethernet: Altera TSE MAC version 15.0 at 0xff200000 irq 72/73 

altera_tse ff200000.ethernet eth0: Could not find the PHY 

altera_tse ff200000.ethernet eth0: Cannot attach to PHY (error: -19) 

altera_tse ff200000.ethernet (unregistered net_device): MDIO bus altera_tse-0: removed 

altera_tse ff201000.ethernet: Altera TSE MAC version 15.0 at 0xff201000 irq 75/76 

altera_tse ff201000.ethernet eth0: Could not find the PHY 

altera_tse ff201000.ethernet eth0: Cannot attach to PHY (error: -19) 

 

But either in the sources nor in the www I can find anything about error -19 

After booting the network is not listed under "ip addr", too. 

 

Where can I search for the problem? 

Where do I get more information? 

Where is my problem? 

How can I check if the bridge between hps and fpga is set up correct? 

--- Quote End ---  

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