I have on my board a SRAM and a NVRAM device that share a common set of pins for address, data, r/w. CE are separate. Each device has different timing parameters. The NVRAM operates at ~4x slower than the SRAM.
It is easy enough to set up two tri-state slaves in SOPC with appropriate timing but combining the interfaces at the top level FPGA is not intuitive. Do I need to drop them as tri-state slaves and create individual MM slaves and then create a block of logic in at the top level to mux and create wait states for the different interfaces and take appropriate tri-state measures? Or is there an easier way to manage this?
