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About mSGDMA core settings

daimatsu_kiki
Beginner
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I have a project in Quartus 18.0 that incorporates Nios2 for Cyclone IVE.

In this project, packets received over Triple-Speed Ethernet are forwarded to an external SDRAM via mSGDMA.

There is a setting in the mSGDMA core configuration that I don't understand: what is the 'Maximum Transfer Length' parameter in the mSGDMA core for transferring what data from where to where?(User Guide: UG-0185  Chapter.30  'Modular Scatter-Gather DMA core')

I thought this was a parameter for transferring incoming packets from mSGDMA to SDRAM, but when I checked with Signal Tap it seems to be different.When the FPGA receives a 1518-byte packet with 'Maximum Transfer Length=1KB', mSGDMA seems to transfer all the packet data to SDRAM in a single transfer.I would have expected the transfer to SDRAM to be split into two transfers.

Could you please tell me what the 'Maximum Transfer Length' setting is?

 

P.S. mSGDMA is Memory-Mapped to Streaming mode and prefetcher enabled.

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JingyangTeh
Employee
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Hi


The Maximum Transfer Length parameter is the maximum length a data could be stored in a descriptor.

A descriptor sets up the transfer parameters for a DMA channel transfer. If in general the data you are passing is smaller you could set this parameter to be smaller to increase the performance.


Regards

Jingyang, Teh


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daimatsu_kiki
Beginner
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Thank you for your answer.


Maximum Transfer Length parameter is the maximum value that can be set in the length field of the descriptor, isn't it?


For example, when the FPGA receives a 1518-byte packet with 'Maximum Transfer Length=1KB', will the mSGDMA controller create two descriptors?
(Descriptor 1: Length = 1024,
Descriptor 2: Length = 494)


Regards

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JingyangTeh
Employee
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Hi


Yes. This is correct.


Regards

Jingyang, Teh


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