Accesing Character LCD

Altera_Forum · ‎02-05-2016

Hi,

I have Problems, Accesing a Character Display wit NIOSII.

I´m using the 16x2 Character Display IP from the University Programm.

I have wired R/W to ground, so that I only can perform Write operations to the Display.

Could this be a Problem?

Here is my my main Code:

# include <stdio.h># include <unistd.h># include "system.h"# include "altera_avalon_pio_regs.h"# include "altera_up_avalon_character_lcd.h"
int main()
{ 
    printf("working!\n");
    alt_8 count = 0;
    alt_up_character_lcd_dev * char_lcd_dev;
    // open the Character LCD port
    char_lcd_dev = alt_up_character_lcd_open_dev("/dev/lcd");
    if
    ( char_lcd_dev == NULL)
    {
    printf ("Error: could not open character LCD device\n");
    printf(char_lcd_dev);
    }
    else
    printf ("Opened character LCD device\n");
    /* Initialize the character display */
    alt_up_character_lcd_init (char_lcd_dev);
    /* Write "Welcome to" in the first row */
    alt_up_character_lcd_string(char_lcd_dev, "Welcome to");
    /* Write "the DE2 board" in the second row */
    char second_row = "the DE2 board\0";
    alt_up_character_lcd_set_cursor_pos(char_lcd_dev, 0, 1);
    alt_up_character_lcd_string(char_lcd_dev, second_row);
  /* Event loop never exits. */
  while (1)
  {
      IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,count);
      usleep(100000);
  }
  return 0;
}

When I try it, char_lcd_dev is NULL.

I get This Message via JTAG-UART:


working!
Error: could not open character LCD device
4

In Qsys the lcd is named lcd, so i think "/dev/lcd" is correct.

You can see a screenshot of my Qsys Sytem as Attachment.

Or here in higher Resolution:

http://abload.de/image.php?img=displayqsysr5jmu.png

This is my system.h:

# ifndef __SYSTEM_H_# define __SYSTEM_H_
/* Include definitions from linker script generator */# include "linker.h"
/*
 * CPU configuration
 *
 */
# define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"# define ALT_CPU_BIG_ENDIAN 0# define ALT_CPU_BREAK_ADDR 0x00010820# define ALT_CPU_CPU_ARCH_NIOS2_R1# define ALT_CPU_CPU_FREQ 50000000u# define ALT_CPU_CPU_ID_SIZE 1# define ALT_CPU_CPU_ID_VALUE 0x00000000# define ALT_CPU_CPU_IMPLEMENTATION "tiny"# define ALT_CPU_DATA_ADDR_WIDTH 0x11# define ALT_CPU_DCACHE_LINE_SIZE 0# define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0# define ALT_CPU_DCACHE_SIZE 0# define ALT_CPU_EXCEPTION_ADDR 0x00008020# define ALT_CPU_FLASH_ACCELERATOR_LINES 0# define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0# define ALT_CPU_FLUSHDA_SUPPORTED# define ALT_CPU_FREQ 50000000# define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0# define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0# define ALT_CPU_HARDWARE_MULX_PRESENT 0# define ALT_CPU_HAS_DEBUG_CORE 1# define ALT_CPU_HAS_DEBUG_STUB# define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION# define ALT_CPU_HAS_JMPI_INSTRUCTION# define ALT_CPU_ICACHE_LINE_SIZE 0# define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0# define ALT_CPU_ICACHE_SIZE 0# define ALT_CPU_INST_ADDR_WIDTH 0x11# define ALT_CPU_NAME "cpu"# define ALT_CPU_OCI_VERSION 1# define ALT_CPU_RESET_ADDR 0x00008000
/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */
# define NIOS2_BIG_ENDIAN 0# define NIOS2_BREAK_ADDR 0x00010820# define NIOS2_CPU_ARCH_NIOS2_R1# define NIOS2_CPU_FREQ 50000000u# define NIOS2_CPU_ID_SIZE 1# define NIOS2_CPU_ID_VALUE 0x00000000# define NIOS2_CPU_IMPLEMENTATION "tiny"# define NIOS2_DATA_ADDR_WIDTH 0x11# define NIOS2_DCACHE_LINE_SIZE 0# define NIOS2_DCACHE_LINE_SIZE_LOG2 0# define NIOS2_DCACHE_SIZE 0# define NIOS2_EXCEPTION_ADDR 0x00008020# define NIOS2_FLASH_ACCELERATOR_LINES 0# define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0# define NIOS2_FLUSHDA_SUPPORTED# define NIOS2_HARDWARE_DIVIDE_PRESENT 0# define NIOS2_HARDWARE_MULTIPLY_PRESENT 0# define NIOS2_HARDWARE_MULX_PRESENT 0# define NIOS2_HAS_DEBUG_CORE 1# define NIOS2_HAS_DEBUG_STUB# define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION# define NIOS2_HAS_JMPI_INSTRUCTION# define NIOS2_ICACHE_LINE_SIZE 0# define NIOS2_ICACHE_LINE_SIZE_LOG2 0# define NIOS2_ICACHE_SIZE 0# define NIOS2_INST_ADDR_WIDTH 0x11# define NIOS2_OCI_VERSION 1# define NIOS2_RESET_ADDR 0x00008000
/*
 * Define for each module class mastered by the CPU
 *
 */
# define __ALTERA_AVALON_JTAG_UART# define __ALTERA_AVALON_ONCHIP_MEMORY2# define __ALTERA_AVALON_PIO# define __ALTERA_AVALON_TIMER# define __ALTERA_NIOS2_GEN2# define __ALTERA_UP_AVALON_CHARACTER_LCD
/*
 * System configuration
 *
 */
# define ALT_DEVICE_FAMILY "MAX 10"# define ALT_ENHANCED_INTERRUPT_API_PRESENT# define ALT_IRQ_BASE NULL# define ALT_LOG_PORT "/dev/null"# define ALT_LOG_PORT_BASE 0x0# define ALT_LOG_PORT_DEV null# define ALT_LOG_PORT_TYPE ""# define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0# define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1# define ALT_NUM_INTERRUPT_CONTROLLERS 1# define ALT_STDERR "/dev/null"# define ALT_STDERR_BASE 0x0# define ALT_STDERR_DEV null# define ALT_STDERR_TYPE ""# define ALT_STDIN "/dev/null"# define ALT_STDIN_BASE 0x0# define ALT_STDIN_DEV null# define ALT_STDIN_TYPE ""# define ALT_STDOUT "/dev/jtag_uart"# define ALT_STDOUT_BASE 0x11030# define ALT_STDOUT_DEV jtag_uart# define ALT_STDOUT_IS_JTAG_UART# define ALT_STDOUT_PRESENT# define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"# define ALT_SYSTEM_NAME "NIOS_sys"
/*
 * hal configuration
 *
 */
# define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API# define ALT_MAX_FD 4# define ALT_SYS_CLK none# define ALT_TIMESTAMP_CLK none
/*
 * jtag_uart configuration
 *
 */
# define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart# define JTAG_UART_BASE 0x11030# define JTAG_UART_IRQ 0# define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0# define JTAG_UART_NAME "/dev/jtag_uart"# define JTAG_UART_READ_DEPTH 64# define JTAG_UART_READ_THRESHOLD 8# define JTAG_UART_SPAN 8# define JTAG_UART_TYPE "altera_avalon_jtag_uart"# define JTAG_UART_WRITE_DEPTH 64# define JTAG_UART_WRITE_THRESHOLD 8
/*
 * lcd configuration
 *
 */
# define ALT_MODULE_CLASS_lcd altera_up_avalon_character_lcd# define LCD_BASE 0x11038# define LCD_IRQ -1# define LCD_IRQ_INTERRUPT_CONTROLLER_ID -1# define LCD_NAME "/dev/lcd"# define LCD_SPAN 2# define LCD_TYPE "altera_up_avalon_character_lcd"
/*
 * led_pio configuration
 *
 */
# define ALT_MODULE_CLASS_led_pio altera_avalon_pio# define LED_PIO_BASE 0x11020# define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0# define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0# define LED_PIO_CAPTURE 0# define LED_PIO_DATA_WIDTH 5# define LED_PIO_DO_TEST_BENCH_WIRING 0# define LED_PIO_DRIVEN_SIM_VALUE 0# define LED_PIO_EDGE_TYPE "NONE"# define LED_PIO_FREQ 50000000# define LED_PIO_HAS_IN 0# define LED_PIO_HAS_OUT 1# define LED_PIO_HAS_TRI 0# define LED_PIO_IRQ -1# define LED_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1# define LED_PIO_IRQ_TYPE "NONE"# define LED_PIO_NAME "/dev/led_pio"# define LED_PIO_RESET_VALUE 0# define LED_PIO_SPAN 16# define LED_PIO_TYPE "altera_avalon_pio"
/*
 * onchip_mem configuration
 *
 */
# define ALT_MODULE_CLASS_onchip_mem altera_avalon_onchip_memory2# define ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0# define ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0# define ONCHIP_MEM_BASE 0x8000# define ONCHIP_MEM_CONTENTS_INFO ""# define ONCHIP_MEM_DUAL_PORT 0# define ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"# define ONCHIP_MEM_INIT_CONTENTS_FILE "NIOS_sys_onchip_mem"# define ONCHIP_MEM_INIT_MEM_CONTENT 0# define ONCHIP_MEM_INSTANCE_ID "NONE"# define ONCHIP_MEM_IRQ -1# define ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1# define ONCHIP_MEM_NAME "/dev/onchip_mem"# define ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0# define ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"# define ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"# define ONCHIP_MEM_SINGLE_CLOCK_OP 0# define ONCHIP_MEM_SIZE_MULTIPLE 1# define ONCHIP_MEM_SIZE_VALUE 20480# define ONCHIP_MEM_SPAN 20480# define ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"# define ONCHIP_MEM_WRITABLE 1
/*
 * sys_clk_timer configuration
 *
 */
# define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer# define SYS_CLK_TIMER_ALWAYS_RUN 0# define SYS_CLK_TIMER_BASE 0x11000# define SYS_CLK_TIMER_COUNTER_SIZE 32# define SYS_CLK_TIMER_FIXED_PERIOD 0# define SYS_CLK_TIMER_FREQ 50000000# define SYS_CLK_TIMER_IRQ 1# define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0# define SYS_CLK_TIMER_LOAD_VALUE 49999# define SYS_CLK_TIMER_MULT 0.001# define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"# define SYS_CLK_TIMER_PERIOD 1# define SYS_CLK_TIMER_PERIOD_UNITS "ms"# define SYS_CLK_TIMER_RESET_OUTPUT 0# define SYS_CLK_TIMER_SNAPSHOT 1# define SYS_CLK_TIMER_SPAN 32# define SYS_CLK_TIMER_TICKS_PER_SEC 1000# define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0# define SYS_CLK_TIMER_TYPE "altera_avalon_timer"
# endif /* __SYSTEM_H_ */

I think the IP Core is working and the Display is wired correct, because the Cursor of the Display is blinking.

Greets

Olaf

Altera_Forum · ‎02-05-2016

When in doubt, verify. Check DB7-DB0 and E signals to verify the initialization values are being sent to the LCD.

Altera_Forum · ‎02-13-2016

Hello Olaf,

I am a beginner also, but looking at your questions i might be able to shed some light.

If you use a 1602 with an arduino, the arduino is also configured in a way that it can only write to the 1602 and not read. Hence i do not think that being unable to read is the cause of your problem.

I am working on a nios II project with an 16550 uart. In my device, i am able to open my 16550 uart device correctly and obtain a pointer to a device like structure.

Points of attention:

- configure / compile QSYS correctly (name of the device)

- generate BSP correctly (each and every time you modify qsys) right clikc on bsp project / select NiosII / Generate BSP

- rebuild both project bsp and your main project.

- if you trace into the source code of the system (start debug in nios ii using te bullet butten left of the run (play button) + F5 step into and F6 step over) at a certain point you will find a series of compares from your device name to the device names available in your qsys system. Here you can see if you have made a typing error or if the lcd device is not available at all.

Best Regards,

John

NIOS II beginner.