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Access On-Chip memory from NIOS and custom logic

Honored Contributor II

Hello everyone. 


I am working on an embedded control system running on a Cyclone IV FPGA. The control algorithm (custom FPGA logic) reads values (16 bit integers) from a pre-computed (offline) Look-Up-Table.  

A new data sample will only be needed every 1/10 of a millisecond (Ts = 1e-4 s) 


I decided to utilize the on-chip memory (M9k) blocks since a.) this offers the lowest latency and b.) the size of the memory should be sufficient.  


The system should do the following: 

- At power-up read data from flash and store it to the on-board memory  

- Allow custom FPGA logic to read this data (no write only read) 


What would be the best way to implement this? I would incorporate the flash storage in QSYS and then write a C-program for the NIOS II processor to facilitate the task of filling the On-Chip memory at start-up. The on-chip memory should be configured in dual-port mode.  


From here I have some questions... 


Is it possible to simultaneously access the on-chip memory in my custom logic through megafunctions?  

Would it be better to use a custom QSYS component and access the memory via the Avalon-MM interface and afterwards provide the data to the outside FPGA logic via Avalon-Conduit interface? 

Is there something fundamentally wrong with this approach? 


I would really appreciate your expertise.
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2 Replies
Honored Contributor II

1) You could get the fpga hardware initialise to load your memory block - then you only need a single read interface to the memory block. 

2) IIRC qsys can instantiate a memory block with the 'other' port directly exposed (so you can use the simple M9K interface instead of an Avalon master one that gets collapsed down because most of the signals aren't needed). 

3) You should be able to link the data with your nios program and then get whatever loads your Nios code to load the data to the correct memeory block. Read up on linker scripts and __attribute__((section("name"))). 


If you do write the data from the Nios (directly or indirectly via the bootloader) do make sure the data gets past any data cache.
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Honored Contributor II

Thanks for the hints. I am looking into your suggestions once at a time. 



--- Quote Start ---  

1) You could get the fpga hardware initialise to load your memory block - then you only need a single read interface to the memory block. 

--- Quote End ---  



I am assuming you refer to the Memory Initialization File (.mif) ? 


I like the idea b/c I could create this file with a script in Matlab. What happens when a reset is performed, will the memory blocks be initialized again ? 

Eventually there will be a NIOS II system for state machine purposes etc. regardless of how the control dedicated memory will be loaded. In case I am using parts of the On-Chip memory with the NIOS II, I assume I have to be very careful with the address range I specify b/c otherwise NIOS II will override some of my memory.  

The dedicated memory should be configured as ROM, it is very important that the stored values remain unchanged. 

Anything else I have to watch out for if I go with this approach?
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