Arria 10 fPLL lock problem

Altera_Forum · ‎04-10-2018

Hi all,

I have a design that uses the fPLL in Core mode (transceivers are not used) to generate some clocks,

the problem is that it never finishes the calibration, pll_cal_busy stays high;

I have a 125MHz USRCLK and the reference clock is also connected to the fPLL dedicated clock input pins,

The question is; do I need the calibration for Core mode? If not how to turn it off? What could cause the calibration to fail?

Thanks in advance for any advice,

Jakab

Altera_Forum · ‎04-10-2018

Hi,

Maybe because of reset.

Have you reset the PLL?Use pll_powerdown to reset.

If you don't want the pll_cal_busy then use CMU PLL.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎04-11-2018

Hi,

Thank you for the reply.

Adding a reset didn't solve the problem; I disabled the fPLL reset-calibration link with:

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1"

and now the PLL locks. pll_cal_busy was keeping the PLL in reset.

pll_cal_busy is still active so the question remains:

Do I need the calibration for the fPLL to work correctly in "Direct" mode?

Best regards,

Jakab

Altera_Forum · ‎05-07-2018

Hi,

Apologies for the late response.

Calibration is not required.

I have checked with Reference clock frequency of 40MHz and output clock frequency of 24MHz.

Also checked with Reference clock frequency of 150MHz and output clock frequency of 50MHz

The pll_cal_busy signal goes low after 580 ns and pll_locked is asserted.

Also, check below link may be it helps.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)