Hello:
I'm atempting to add a SRAM to a NIOS II Cyclone CPU.
THe SRAM is an ST M86AW256M (16 bit data) and uses signals UBn and LBn.
These are Upper Byte and Lower Byte Enabled.
THe logic to read and write the SRAM requires that one or both of these signals to go active.
I've created an interface to user logic with SOPC builder and added 2 'byteenable_n' type signals as ports.
My questions is where can I find the logic and timing descriptions for these signals.
I've searched byte enable but can't find what I'm looking for.
George
