Boot problem on Altera DSP_stratixII_2s60_ES

Altera_Forum · ‎03-21-2005

Hi, everyone

I was successfully configuring, building, uploading and booting the uClinux on my Altera DSP Development Kit, Stratix II Edition.

Is there any special consideration about this kit?

Such as no corresponding device option on platform dependant setup in the newest 1.3 version....

I've modify my .config to thosburke's new one.

Still got same problem about "..can't find mtdblock0.."

Here is the boot screen:

Thanks in advance,

Thomas

Altera_Forum · ‎03-22-2005

what kind of flash is there on this board? Maybe you can try enabling CONFIG_MTD_JEDECPROBE.

Altera_Forum · ‎03-23-2005

Thank you,

It's AMD's Am29LV128MH,

and I've tried this configuration already...

Altera_Forum · ‎03-23-2005

Probably you need some customization ( we don't have a board with this kind of flash here). If you are willing to try, I have two solutions for you:

1. If you don't want the capability to write flash under uClinux (such as required by jffs2), I can email you a rom map, and you will be able to use romfs. Please tell me an email address if you like.

2. If you want the kernel find out the flash you are using, so that you can use jffs2 later, you need to do this:

1) enable CONFIG_MTD_JEDECPROBE, since Am29LV128MH is a jedec standard chip.

2) Since this chip's bus width is 16 bit (better check me on this), you need to change the Altera NDK map (drivers/mtd/maps/altera.c), change the line

#define BUSWIDTH 1

to:

#define BUSWIDTH 2

3) Add the chip infor to the jedec_table[] in file /drivers/mtd/chips/jedec_probe.c, like Microtronix did for AM29LV065D. You have to find the necessary information from the datasheet of that chip.

Then the kernel should be able to find the chip.

Good luck,

wentao

Altera_Forum · ‎03-26-2005

Good day~~

The 1.3 version of uClinux has no problem with the Am29LV128MH flash chip.

I just change to the Nios II Development Kit, Stratix II Edition, which has the same flash chip as DSP Development Kit, Stratix II Edition. And everything goes well.

My guess is that the board design of DSP Development Kit, Stratix II Edition (especially the CPLD configuration) causes above problem. I will keep trying.

Thanks to wentao ^^