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Can't synthesize Nios II without IP license

Altera_Forum
Honored Contributor II
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I'm trying to evaluate a Nios II design using Quartus II 11.1 sp1. I get the following error from Quartus: 

 

 

Error (204012): Can't generate netlist output files because the file <file> is an OpenCore Plus time-limited file 

 

The KB says to turn off IBIS file generation to fix this but it's not on. 

 

All the documentation says that I should be able to evaluate a Nios II core without having to buy the license first.
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Altera_Forum
Honored Contributor II
388 Views

 

--- Quote Start ---  

I'm trying to evaluate a Nios II design using Quartus II 11.1 sp1. I get the following error from Quartus: 

 

 

Error (204012): Can't generate netlist output files because the file <file> is an OpenCore Plus time-limited file 

 

The KB says to turn off IBIS file generation to fix this but it's not on. 

 

All the documentation says that I should be able to evaluate a Nios II core without having to buy the license first. 

--- Quote End ---  

 

 

You can.  

 

Does the overall compile give you Success?  

 

Which file is it?
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Altera_Forum
Honored Contributor II
388 Views

You've disabled core evaluation option. It's somewhere deep in project options...

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Altera_Forum
Honored Contributor II
388 Views

 

--- Quote Start ---  

You can.  

 

Does the overall compile give you Success?  

 

Which file is it? 

--- Quote End ---  

 

 

No, it does not. It doesn't even try to fit the design. Just a bunch of these errors. I'm using the free web version of Quartus. Does that make a difference?
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Altera_Forum
Honored Contributor II
388 Views

The "Disable OpenCore Plus hardware evaluation" option is set to OFF.

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Altera_Forum
Honored Contributor II
388 Views

Nope.  

 

I use free version too. No problems.  

 

Are you using a non Altera IP core in your design?  

 

Tools -> license setup and be sure to include IP core license there.
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Altera_Forum
Honored Contributor II
388 Views

 

--- Quote Start ---  

Nope.  

 

I use free version too. No problems.  

 

Are you using a non Altera IP core in your design?  

 

Tools -> license setup and be sure to include IP core license there. 

--- Quote End ---  

 

 

No, it's just a Nios II with RAM and DMA. No other IP.
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Altera_Forum
Honored Contributor II
388 Views

Hmmm  

 

Try assignments - > Settings -> EDA Tools settings.  

 

Make sure the Tool names are set to none. I wonder if it is trying to generate a netlist for that.
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Altera_Forum
Honored Contributor II
388 Views

i'm guessing its EDA Netlist Writer giving that error. i don't think you can generate a chip simulation netlist without a license

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Altera_Forum
Honored Contributor II
388 Views

 

--- Quote Start ---  

Hmmm  

 

Try assignments - > Settings -> EDA Tools settings.  

 

Make sure the Tool names are set to none. I wonder if it is trying to generate a netlist for that. 

--- Quote End ---  

 

 

Yes, that was it. I had ModelSim-Altera selected for simulation and setting it to "none" fixed the problem. Thanks to everyone for their help.
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Altera_Forum
Honored Contributor II
388 Views

I had the same problem with my quartus II 11.1. Now I have fixed it. Thanks to rob18767

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Altera_Forum
Honored Contributor II
388 Views

Thanks, this post helped me.

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