Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.
12578 Discussions

Complile error on NIOS II - `onchip_ram' overflowed

Altera_Forum
Honored Contributor II
1,419 Views

Hi all  

 

I am new in the Altera Cyclone V FPGAs and i'm doing the tutorials provided with the BEMicro SDK and i have managed to urn the image onto the chip. The problem i am having is is of the following nature.  

 

c:/altera/12.0/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/bin/ld.exe: bemicro_led_control.elf section `.text' will not fit in region `onchip_ram' 

c:/altera/12.0/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/bin/ld.exe: region `onchip_ram' overflowed by 19784 bytes 

collect2: ld returned 1 exit status 

make: *** [bemicro_led_control.elf] Error 1 

 

Could you help as i am stuck on this part now.  

 

Kind regards
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
685 Views

The problem is quite clear: your project doesn't fit into onchip ram. 

Solutions: 

- if your fpga has enough spare memory resource, increase onchip ram dimension,  

- remove any unnecessary big variables, especially strings and long arrays 

- avoid use of code consuming library functions, like printf and floating point management 

- compile in release mode instead of debug
0 Kudos
Reply