Custom Instructions and fmax

[Altera_Forum]

I've developed a extended multicycle custom instruction as a finite state machine in order to avoid a high max tpd. In a separated project (only the vhdl code), the ci reachs fmax to up 150 MHz, however when I insert it into a cpu in another project, this latter, which used to run under 100 MHz now runs under 74 MHz. In Quartus compilation report I've notice that this delay is due to wires between cpu custom instruction and the cpu component. 

I've already tried to optimize the hdl code and use many performance optimization on Quartus settings, but I had no success. Not even pipelining clock in Sopc Builder increased the fmax. Does somebody has suggestions?  Thanks a lot. Mendonca

[Altera_Forum]

--- Quote Start ---  originally posted by mendonca@Mar 8 2007, 09:34 AM i&#39;ve developed a extended multicycle custom instruction as a finite state machine in order to avoid a high max tpd. in a separated project (only the vhdl code), the ci reachs fmax to up 150 mhz, however when i insert it into a cpu in another project, this latter, which used to run under 100 mhz now runs under 74 mhz. in quartus compilation report i&#39;ve notice that this delay is due to wires between cpu custom instruction and the cpu component. i&#39;ve already tried to optimize the hdl code and use many performance optimization on quartus settings, but i had no success. not even pipelining clock in sopc builder increased the fmax. does somebody has suggestions?  thanks a lot. mendonca <div align='right'><{post_snapback}> (index.php?act=findpost&pid=22119)  --- quote end ---    --- Quote End ---     I&#39;m assuming this is the only custom instruction that you have added to the Nios II core. Since you are having Fmax issues be sure to pipeline your "result" and "done" signals. Now if you have many custom instructions then you should consider condensing them into a single custom instruction and using the "n" signal as your CI select. If you are using the Nios II &#39;s&#39; core you may have better luck using the &#39;f&#39; core since the extra pipeline stage helps the timing.