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Hello ,
I am using a Cyclone 10 GX with Nios V and the Micrium MicroC/OS-II operating system. My setup includes the Triple-Speed Ethernet Intel FPGA IP paired with the Modular Scatter-Gather DMA Intel FPGA IP, connected to a DP83620 PHY IC.
Problem Description:
In my implementation, the auto-negotiation completes successfully, and the link is established as indicated by the PHY status registers.
I have configured an IPv4 address, subnet mask, and gateway using NetIPv4_CfgAddrAdd. Additionally, the socket() creation, bind(), and listen() calls in my socket server task all succeed without errors.
However, the system does not respond to ping requests from a connected PC using the assigned IP address.
Key Information:
The Ethernet MAC and PHY configuration seem correct:
Auto-negotiation and link establishment indicate that hardware connections are likely fine.
The MAC and IP address settings are successfully applied.
The Modular Scatter-Gather DMA is initialized and configured, but there might be a gap in how the RX/TX buffers and descriptors interact with the network stack.
Debugging Steps Taken:
Verified MAC, PHY, and DMA initialization logs.
Confirmed that the socket(), bind(), and listen() functions in the SocketServerTask return no errors.
Observed proper PHY register behavior, including link status and speed/duplex negotiation.
If anyone has experience with a similar setup or can offer suggestions on how to debug further or resolve this issue, I would greatly appreciate your input!
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Hi
I believe you are trying to migrate the NiosII TSE example to the NiosV.
Instead could you try migrating the example design for Arria10 to Cyclone10GX.
The difference between the NiosII and NiosV is one using the Niche TCP/IP stack and another is using the uC TCP/IP stack.
Regards
Jingyang, Teh
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Hi Jingyang,
Thanks for your reply.
Yes, I am using the Arria 10GX example and migrate the code into my cyclone 10GX. I made all the function return no error. But it do not work on Ping or Telnet....
Have you use the TSE on Cyclone10GX before ?
Thanks
Best regards,
Paul
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Hi JingyangTeh,
Thanks for your project.
I wanted to double-check with you regarding the clk_enet_fpga_p pin (AB16). Can this pin be used as a normal I/O(configure normal I/O in your project)? On the schematic, it is marked as an LVDS differential pin. I previously configured it as LVDS, but it seems there is an error indicating that pin AB16 does not support the HSSI reference clock. Could you clarify this?
Additionally, are there any special settings required when generating the BSP?
For reference, I typically enable os_tmr_en and uc_tcp_ip, while leaving other settings at their default values.
Thank you, and I look forward to your response!
Best regards,
Paul
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Hi JingyangTeh,
I have tried your project but it have the error 2010 that I checked that you have faced it before.
and I checked the reset pin already there from the project that you sent to me.
Just see any other think I am missing.
Thanks
Best regards,
Paul
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Hi
Sorry for the late , was OOO for the Lunar New Year.
You would need to generate the BSP base on the steps below:
Regards
Jingyang, Teh
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Hi Jingyang,
Happy Lunar New Year.
Yes, I also follow the Arria 10 example's readme file command to generate the BSP as below, I think it already include the steps in the link you placed in previous post.
Script from the Arria 10 example :
niosv-bsp -c sw/bsp/settings.bsp --sopcinfo=hw/sys.sopcinfo --type=ucosii --cmd="enable_sw_package uc_tcp_ip" --cmd="set_setting altera_avalon_jtag_uart_driver.enable_small_driver {1}" --cmd="set_setting hal.enable_instruction_related_exceptions_api {1}" --cmd="set_setting hal.log_flags {0}" --cmd="set_setting hal.log_port {sys_jtag_uart}" --cmd="set_setting hal.make.cflags_defined_symbols {-DTSE_MY_SYSTEM}" --cmd="set_setting hal.make.cflags_user_flags {-ffunction-sections -fdata-sections -fno-tree-vectorize}" --cmd="set_setting hal.make.cflags_warnings {-Wall -Wextra -Wformat -Wformat-security}" --cmd="set_setting hal.make.link_flags {-Wl,--gc-sections}" --cmd="set_setting ucosii.miscellaneous.os_max_events {80}" --cmd="set_setting ucosii.os_tmr_en {1}" --cmd="set_setting hal.make.cflags_optimization {-O2 -fno-tree-vectorize}"
Based on your example of migrating from Arria 10 to Cyclone 10 GX, could you help confirm whether the clk_enet_fpga_p pin (AB16) can be used as a regular I/O pin instead of LVDS, as I mentioned in my previous post?
Additionally, do you have any insights on error 2010? I have already checked the reset pin in the project you sent me, and it appears to be present.
Thanks
Best regards,
Paul
Thanks
Best regards,
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Hi Jingyang,
I successfully downloaded the Quartus project from your earlier post and was able to ping the IP using the Cyclone 10GX development kit.
Now, I am working on a custom Cyclone 10GX board and have transitioned from Nios II (it works properly) to Nios V, making the necessary modifications to the software. However, despite these changes, I am unable to ping the IP.
In my custom Cyclone 10GX board, I am using the DP83620 PHY IC. Due to this, the Ethernet core variation has been changed to 10/100/1000Mb Ethernet MAC, as the chip does not support SGMII. Instead, I am using MII for communication.
Attached are:
- The module configuration in the platform designer
- The modified software code
Auto-negotiation and link establishment appear to be successful, but the board still cannot ping. I would appreciate any insights or suggestions on what I can try to resolve this issue.
Thanks in advance for your help!
Best regards,
Paul
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Hi
It seems like the PHY that you are using is not under the supported list of PHY for the TSE.
You would need to add in the profile for the PHY you are using into the TSE using the method below:
https://www.intel.com/content/www/us/en/docs/programmable/683402/24-3/phy-definition.html
Regards
Jingyang, Teh
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Hi JingYang,
Thanks for your information and I have added the profile for the PHY and change the memory allocation of the DMA module and I can ping the IP now.
Best regards,
Paul
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Hi JingYang,
As we use a different PHY IC in the next hardware version, which utilizes the RGMII interface. I would like to confirm whether the TSE in Cyclone 10GX does not support RGMII. If it does not, is there any way to adapt it to an RGMII PHY IC?
Thanks
Best regards,
Paul

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