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Cyclone III - Timing Constraints Issue

riba
Beginner
506 Views

I encountered an issue with softcore firmware and FPGA setup on a Cyclone III device. Previously, I had been experiencing problems with FPGA synthesis, particularly in meeting timing constraints.

Interestingly, I observed that when the chip's temperature reached 65 degrees Celsius, the firmware began exhibiting suspicious behavior, resulting in incorrect reading and writing operations on dedicated memories.

Since then, I have successfully resolved the timing constraints issue, and it seems that I can no longer replicate the reading/writing problem. The chip now behaves as expected.

My primary question pertains to the potential relationship between FPGA timing and suspicious behavior in reading/writing. With the timing issue resolved, is it reasonable to assume that similar problems will not reoccur?

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Nurina
Employee
464 Views

Hi,


Since you have solved your timing issue and are seeing hardware is working as expected, similar problems won't occur.


It is important to ensure your timing constraints correctly describes the timing paths and that the timing violations are solved in all corners of the FPGA. This is to ensure the hardware works as expected.


Regards,

Nurina


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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Nurina
Employee
417 Views

Hi,


We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

Please let me know of any inconvenience so that I may improve your future service experience.

 

Have a great day!


Best regards,

Nurina


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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riba
Beginner
404 Views

Hi,

 

Could it be possible that we are experiencing one of the issues from this document -> https://statics.teams.cdn.office.net/evergreen-assets/safelinks/1/atp-safelinks.html,  either:

-M9K Memory Block Read Issue

-External Memory Specification for DDR2 SDRAM

 

Can you confirm that this is possible and how could it be fixed?

Thanks

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