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Cyclone V FPGA to HPS at high frequencies

Honored Contributor II

Hi everybody, 

I'm more of a programmer in C/C++, I might need to get started with FPGAs for a university project but it depends if the dev board I checked is applicable for my setup. 

I need to interface a sensor to a PC, I'd prefer to use a standard Gigabit Ethernet interface but as realtime-capability is less needed than reliability I'd rather use TCP than a UDP core running on the FPGA. 


The sensor delivers data at up to 5 MHz, each measurement is 70 bits wide and there is an additional clock signal as a trigger. 

I found the following board by Terasic: with a Cyclone V SoC 

It has 72 GPIO pins which would exactly fit my needs. 


My roadmap would be to do the following: 

setup a Linux on the ARM-A9 in the HPC 

use an Avalon MM master to transfer the incoming 70 bits to a ring buffer in memory (as 3 32 bit words) -> 9 MHz frequency 

on the Linux side implement a daemon that checks for the amount of data buffered and send it when the maximum transmission unit for Ethernet is reached. 


Sounds legit, doesn't it? 

Is there any bottlenecks I should take into consideration? Is it realistic to implement a project like this as someone new to FPGA development? 


Best regards
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Honored Contributor II

Sounds about right. If the trigger comes in at a rate of 5MHz then I would use that to capture the samples then make them available through a memory mapped interface connected to the HPS which software can pull the data out. 


The other idea closer to yours would be to send the samples into a DMA engine which then writes them into HPS memory. That approach will have less overhead since the hardware does the heavy lifting. There are a couple of DMA engines you could use for this, I recommend using the modular SGDMA in ST-to-MM mode. That DMA engine is available in 14.0 but if you are using older tools you can grab it here: You would use that periodic strobe signal to write the 70-bit data into the DMA (use a 128-bit DMA and pad the upper bits) and it would be responsible for writing the 128-bit data into memory. Alternatively you can serialize the data so that you don't have all that wasted memory due to padding but given that 70 bits isn't a nice power of two I don't think it's worth it given all the SDRAM you have connected to the HPS.
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