Error: Peak virtual memory when compile NIOS design file

Altera_Forum · ‎03-03-2016

Hi everyone,

I get a error when I compile a block diagram design file.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11923&stc=1

I think there are some error of my design, but I can't find it. How can I solve the problem?

http://www.alteraforum.com/forum/attachment.php?attachmentid=11924&stc=1 http://imgur.com/zpukmxy

I just connect the I/O to the correspond pin.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11925&stc=1

Many Thanks

Altera_Forum · ‎03-04-2016

What are the 8 errors Quartus is reporting? Pasting those into the post might help...

Cheers,

Alex

Altera_Forum · ‎03-04-2016

I didn't realize that there are more errors above that error. Now the error is solved. Thanks for the reply, Alex.

However, would you like to help me to check another error of my design? I want to deal with the audio codec in FPGA but I can't even get any echo for now...

Many Thanks