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Ethernet on 3C120

Altera_Forum
Honored Contributor II
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Hi, 

Does anybody manage to make the TSE run under uClinux ? I try what I read on the wiki, but I can't get a ping from or to the dev board (FPGA Dev kit 3c120). 

Do I have to use the opencore 10/100 MAC ? 

 

Thank you in advance.
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Altera_Forum
Honored Contributor II
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Hey, 

 

In fact, I don't care about the type of the dev board....  

 

Does anybody manage to use the Marvell PHY 88E1111 with a Altera Triple Speed Ethernet MAC under uClinux ? 

 

Thanks
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Altera_Forum
Honored Contributor II
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Ok I have implemented the Opencore 10/100 MAC in my design today, and it doesn't work. 

LED are blinking right when I ping the board, counter of data (rx and tx) in ifconfig are well incremented but there are no answer.  

Does anybody got a schematic of the Opencore 10/100 MAC with a Marvell PHY 88E1111?  

 

ideas : I am not sure on how to wire Tx_Clk and gtx_clk .... 

 

Regards,
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Altera_Forum
Honored Contributor II
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Hello, 

i've had the same problem on 3C120 that will be my next working board and for now, don't solve it under uClinux. 

 

For my test i'm working with the 2c35 where eth works out of the box... 

 

What i've seen : 

- ping from a PC : Tx and Rx Led OK (+packet count in ifconfig eth0) 

- ping from the board (lo or eth0) ping OK, but no leds activity (OK, it use loopback) 

- ping a PC from the board : nothing... 

 

i really don't understand, but i'm just "high level software" developper (c/c++,...) not VHDL/verilog... 

 

if you have an idea, 

thx, FP
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Altera_Forum
Honored Contributor II
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Hi everybody, 

 

Nobody manage to use the ethernet connection on 3c120 dev kit ? 

 

PS: Guru, could you help us ? please...
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Altera_Forum
Honored Contributor II
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Maybe this will help, it's part of bdf file of CIII 3c120 with marvell 88e1111 

100 mbit only
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Altera_Forum
Honored Contributor II
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Hi dim99, 

 

Thanks for you answer. Does the ethernet works on your 3c120 dev kit ? Which driver do you use under uClinux (The TSE SLS, or the TSE Experimental) ? 

 

Regards, 

 

------------------------------------------------------ 

from France with love...
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Altera_Forum
Honored Contributor II
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Yes it works, but now only transmit, a have some problems with receive packet. 

I can't enter isr from sgdma. 

 

p.s. i don't use Uclinux ) 

i have the only PHY+MAC for tx\rx
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Altera_Forum
Honored Contributor II
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what is the clk_25khz2 that you enter in tx_clk_to_the_tse_mac ? 

is it the clk_25khz1 exactly ? 

 

 

The RX is work for me but not the tx...  

You don't use any OS ?
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Altera_Forum
Honored Contributor II
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clk_25khz1 - 25 mhz from eth_pll with phase = 0; 

clk_25khz2 - 25 mhz from eth_pll with phase =180.00; 

 

In some articles or on forum i read that it has to be done the differences between the phase, but maybe i'am wrong. 

 

No, i don't use any OS. 

So, can you show your pins to TSE? 

If your rx works maybe i'am wrong in some moments with rx.
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Altera_Forum
Honored Contributor II
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IT WORKS !!!! 

 

Thank you very very much. 

 

Spaciba !!! 

 

PS: I will update the wiki
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Altera_Forum
Honored Contributor II
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I'am to hear it ) 

 

And can you show the control of your TSE and software for rx?
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Altera_Forum
Honored Contributor II
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Here is !!! 

Thanks again
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Altera_Forum
Honored Contributor II
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At first sight i have the same signals and pins. 

 

And what about rx software, can you show sode for rx?
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Altera_Forum
Honored Contributor II
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I use uClinux for Rx and TX...  

 

what is sode ?
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Altera_Forum
Honored Contributor II
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Hi. 

It's my mistake not sode, but code. 

I have already solved problem with rx. it was a small error in software.
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Altera_Forum
Honored Contributor II
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thank's for info. I am working on ethernet on 3c120 too

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Altera_Forum
Honored Contributor II
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Hi Actris, 

 

Which driver is selected in your "menuconfig" please ?? 

 

 

[*] Altera Tripple Speed Ethernet support (EXPERIMENTAL) 

 

or maybe this one : 

 

 

[*]Altera Triple Speed Ethernet MAC support(SLS) 

[*]Drivers for Marvell PHYs 

 

Furthermore, I saw in your SOPC Builder design that you named the components as follows : 

 

sgdma_rx, sgdma_tx, tse_mac, descriptor_memory 

 

Did you change some lines in your "config.c" or does it fit perfectly to the code ?? 

 

Thanks for your answer !! 

 

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Altera_Forum
Honored Contributor II
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Hi, 

I am also working on a 3C120 Development board ethernet design on a Nios2 running uClinux.  

 

I am so close to a solution but run into problems with both the "tripple speed ethernet" and the "triple speed ethernet" options. 

 

With the Tripple Speed Ethernet option (the one that is said to work) - I get a build error at atse.c line 1485, saying it cant find the "get_stats" field in the Network Device descriptor. Does anyone know what would cause this? 

 

With the Triple Speed Ethernet option ...the design builds but when I download the terminal reports that the kernel has successfully uncompressed and starting but it just hangs there. If I disable the Triple Speed Mac - the sash shell goes through to prompt. Does anyone know what might cause this sort of effect? 

 

I have been very careful trying to emulate the various example designs for use of the tse_mac in hardware ... and believe I have a good design, except for one question that I see different from working examples to your pictures in this forum. There is a 180 degree phase shift on the 125MHz clocks in the designs here ... BUT when I reverse engineered the verilog of the uCos based webserver design I did not get this hardware picture at all. What I get is a comment that the clock is 180 degrees BUT when you actually open the pll its 90 on the gtx clock and 90 on the rx clock.  

 

The 125MHz rxclk pin is connected to a source synchronous pll which regenerates the 125MHz signal with a 90 degree phase shift and passes it to the SOPC tse_mac rx clock input 

 

Another PLL phase locks up the system clock to produce two outputs ... a 125MHz tx clock to the tse mac at 0 degrees and ther gtx clock at 90 degrees...??? 

 

Also there is an interesting technique on the 125MHz gtx clock output pin where the physical clock is reconstructed with a DDIO - where the clock selects hardwired Positive and negative levels on positive and negative clock edges respectively. I am thinking that this probably allows propogation deelay skew to be controlled more easily in the assignment editor... which may be the reason why there are difficulties in either Rx and Tx in these designs? I dont know...just thinking out loud - it seems a little odd. 

 

Regardless ... the setup is supposed to work for the example (I have not tried it myself - bit probably should)... which makes me think something different here with respect to what you may have? 

 

If anyone can help it would be much appreciated.  

If anyone out there is struggling with this (like me) and wants to collaborate in with text text ... please let me know ... maybe we can help each other?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

I am also working on a 3C120 Development board ethernet design on a Nios2 running uClinux.  

 

With the Tripple Speed Ethernet option (the one that is said to work) - I get a build error at atse.c line 1485, saying it cant find the "get_stats" field in the Network Device descriptor. Does anyone know what would cause this? 

 

With the Triple Speed Ethernet option ...the design builds but when I download the terminal reports that the kernel has successfully uncompressed and starting but it just hangs there. If I disable the Triple Speed Mac - the sash shell goes through to prompt. Does anyone know what might cause this sort of effect? 

 

--- Quote End ---  

 

 

Hi,  

well... I'm working on a Stratix III DSP dev. kit with the same Marvell chip. 

I got it to work only on interniche but now I'd like to make it work with uClinux. 

 

If I use all the default settings, linux boots with no problems (I'm using the no-mmu version for now). 

If I add any of the TSE option (any of the two, the Altera experimental one or the SLS one, no difference) I get the "Uncompressing linux... Now booting" message and then it freezes. 

I have no idea why this doesn't work, but I assume it's not related to the hardware design because the very same design works well with interniche tcp/ip. 

 

Anyone has an idea why this is happening or got the Stratix III to work under uClinux? 

 

Thanks 

Bye 

mantoz
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Altera_Forum
Honored Contributor II
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Hi mantoz, 

 

Did you select the : 

Ethernet (10 ot 100 Mbit) -> Generic Media Independent Interface device support.  

No need to select the : 

PHY Device support and infrastructure -> Drivers for Marvell PHYs. 

 

What size is your zImage ? 

 

bye
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