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External SRAM interface

Altera_Forum
Honored Contributor II
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From the Nios II DK, the two IDT SRAM's (256kB x 16) are set up in 32-bit words. Since our design will only use one SRAM of smaller size (128kB x 16), would I have to import, say a VHDL source, to implement it within SOPC? How can the control signals get tied in with the Avalon bus without having the signals generated as external ports?

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Altera_Forum
Honored Contributor II
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Use Interface to userlogic: 

 

Bus Interface Type: Avalon Memory Slave 

 

select add generic list of ports and edit it to 

the following. 

 

PORT NAME | Width | Direction | Shared | Type 

 

address | 17 | input | yes | address  

write_n | 1 | input | yes | write_n  

read_n | 1 | input | yes | read_n  

writedata | 16 | inout | yes | data 

chipselect_n | 1 | input | --- | chipselect_n  

be_n | 2 | input | yes | byteenable_n  

 

timing: I use 2 wait and 1 hold cycle (can be optimized)
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Altera_Forum
Honored Contributor II
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Thanks for the instructions. One more question, since the SRAM has lower-byte and upper-byte controls, would both be identified as byteenable_n?

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Altera_Forum
Honored Contributor II
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you should get the signals 

 

nnnn_byteenablen[1..0] 

 

where nnnn is the name of your Avalon Tristate Bridge 

 

connect nnnn_byteenablen[0] to \BLE of SRAM 

connect nnnn_byteenablen[1] to \BHE of SRAM
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Altera_Forum
Honored Contributor II
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Thanks for all your help Fischer. I&#39;m starting to getting the hang of it. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

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