FIFO into SOPC PIO

[Altera_Forum]

I'm currently attempting to gather the output from an FFT, and pass it into Nios for processing etc., the output comes in bursts of 8192 12-bit values.  

 The FFT output running into a DCFIFO, width 12-bit, depth 256 words (I only want to use it as a buffer for each value, so I haven't worried too much about the depth), clocked at 50kHz in and 50MHz out. The wrreq signal is controlled by the valid output signal from the FFT, so values only enter the FIFO when a packet is being output. The q output bus is connected to the external connection export of the respective PIO within my Nios SOPC.  Within Nios, I read the values on the PIO while the FFT output is determined to be valid, and the FIFO is determined to not be empty. I've added a count variable to check how many times the values are read within each packet. the problem i'm having, however, is that the pio for the values only seems to be read 35-45 times for each packet, when i should be getting 8192 for the count. Is there any obvious reason why this is happening? I've been using printf() to print the count variable to the console, but as that occurs in between packet transmission, the delays incurred shouldn't really affect the number of times the values are read.  Any ideas?

[Altera_Forum]

I'd guess that the read side of the fifo is being clocked on the 50MHz clock, not by the reads from the nios.

[Altera_Forum]

Oh right, so how would I go about clocking the reads from the Nios rather than the 50MHz?

[Altera_Forum]

Don't use a PIO. Expose the FIFO directly to Nios II so that you will read the correct number of samples out of the FIFO. You can tie the FIFO empty signal to waitrequest to make sure you don't attempt to read nonexistant samples. The FIFO output connects directly to readdata and you pop the FIFO with read and not empty assumimg you are using a lookahead FIFO.