Nios® V/II Embedded Design Suite (EDS)
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Fatal: Error occurred in protected context

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# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Protected: /fusiontestdebugtb/u_DebugApp/\nios2_qsys|enet_pll|altera_pll_i|general[0].gpll~FRACTIONAL_PLL\/inst/<protected> File: nofile# FATAL ERROR while loading design# Error loading design# Error: Error loading design  


I get the error-message given above when I try to load the my design (for altera arriaV FPGA family) in altera-modelsim. 


My design includes couple of megafunctions, nios2 processor. I have included relevant files for the megafunctions, arriaV atom file. Please help me with the error above 


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