- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I need some help with the functions IOWR_32DIRECT and IORD_32DIRECT. I made a component in VHDL which simply copies the input to the output. Using the Nios II and the functions IOWR_32DIRECT and IORD_32DIRECT I intend to "throw" a value in this component and expect it in return the same value. However, the result is totally different. Could anyone help me indicating where is the error? The architecture used has an Nios II, Onchip Memory, JTAG UART and the component that I created. The codes are: VHDL (Component):----------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
----------------------------------------------
ENTITY Copy IS
PORT (dataIn: in STD_LOGIC_VECTOR (31 DOWNTO 0);
dataOut: out STD_LOGIC_VECTOR (31 DOWNTO 0);
write_n, read_n: in STD_LOGIC;
clk, reset: in STD_LOGIC
);
END ENTITY;
ARCHITECTURE CompCopy OF Copy IS
SIGNAL data: STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF(clk'Event and clk='1') then
IF write_n = '1' THEN
data <= dataIn;
END IF;
IF read_n = '1' then
dataOut<= data;
END IF;
END IF;
END PROCESS;
END CompCopy;
C:
# include <stdio.h># include "system.h"# include "io.h"
int main()
{
int i = 1;
IOWR_32DIRECT(COPY_0_BASE, 1, i);
printf("\nValue: %d\n", IORD_32DIRECT(COPY_0_BASE, 1));
return 0;
}
Returned value: 1052681 The "Signals" tab in "Component Editor" are: name interface
signal type
width
direction
dataIn avalon_slave_0 writedata 32 input dataOut avalon_slave_0 readdata 32 output write_n avalon_slave_0 write_n 1 input read_n avalon_slave_0 read_n 1 input clk clock clk 1 input reset reset reset 1 input Thank you very much!
Link Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Some issues i saw:
- reset unused (helps to have at least a default value when reading your register)
- read_n and write_n are low active (compare with 0 instead of 1, or use the high active signals)
- dataOut is pipelined for one cycle, make sure you have defined one read wait state in qsys/hw.tcl
- there is no address bus (qsys spans a only one single 32Bit word register map)
- you are writing to offset 1 (0x4 as byte offset), this is not your (single word) component
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It worked! Thank you very much!
Just one more question: do you know where I can find the description of each signal type, of the "Signals" tab in "Component Editor" (Signal Type)? Thank you- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Good to hear that it is working now, here is something to read about Signals: :-)
The Avalon spec: https://www.altera.com/literature/manual/mnl_avalon_spec.pdf The SOPC user guide: https://www.altera.com/en_us/pdfs/literature/ug/ug_sopc_builder.pdf QSYS in the Quartus II Handbook Volume 1: Design and Synthesis, Chapter 6: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Good to hear that it is working now, here is something to read about Signals: :-) The Avalon spec: https://www.altera.com/literature/manual/mnl_avalon_spec.pdf The SOPC user guide: https://www.altera.com/en_us/pdfs/literature/ug/ug_sopc_builder.pdf QSYS in the Quartus II Handbook Volume 1: Design and Synthesis, Chapter 6: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf --- Quote End --- Thank you very much! =-D

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page