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How the software infers the burst counts over the Avalon-MM interface?

Honored Contributor II


Description: I’m working under a project, which includes my custom IP to communicate over the Avalon-MM interface with NIOS-II /f. My custom IP is structural design and contains following components: Avalon-MM Slave bus, custom single dual-port block memory (separate writes and reads, and set for M10K). The writes supposed to transfer 32-bit data to the 24-bit single clock dual-port block RAM from the NIOS by software, and reads from an external device, such as our custom VGA controller. The custom Avalon-MM implemented in VHDL and has following ports: ADDRESS, CHIP SELECT, BURST COUNT, WRITE DATA, WRITE, READ DATA, READ, WAIT REQUEST, RESPONSE and READ DATA VALID. The VGA Controller just simply reads the data from the block RAM (no Avalon interface). The FPGA target is Cyclone-V, device: 5CSEMA5F31C6; Quartus II Subscription Edition v 15.0; Windows 7. 

Question 1: How the software infers the burst counts over the Avalon-MM interface? I assume, it could be by “for’ or “while” loops in C code. Is that correct? Of course, the custom component and the NIOS have to support burst count modes. This is the one approach I can implement my design to write data into the single clock dual-port block RAM. 

Question 2: Is it worth to implement the writes into the RAM is to create the second Avalon-MM interface such as CSR (Control and Status Register), similar to the DMA or SGDMA? That would include destination address, data length, control and status registers with certain address offsets.  

Question 3: Where I can get the Avalon-MM Slave bus template? Altera wiki doesn’t work for me, there are Verilog-based design and it contains a lot of unnecessary info. I need VHDL. 

Question 4: What would you recommend in my case? Approach described in question 1 or 2? 

Kind Regards, 

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