Nios® V/II Embedded Design Suite (EDS)
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How to configure the break address for Nios II processor?

Honored Contributor II



I am trying to understand how the "break" instruction does work. Actually, according to the "Nios II Processor Reference Guide", the "break" instruction transfers execution to the break handler whose address is specified in Nios II prameter editor. However, in the Nios II parmaeter editor, I have only found Reset Vector and Exception Vector (in Vectors tab). So, when a break instruction is executed what is the address of the next instruction? Is it the Exception vector offset? 


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