Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12627 Discussions

How to generate sof of FPGA when using ROM?

Altera_Forum
Honored Contributor II
1,107 Views

My design has embeded a ROM of 4096bytes inside FPGA. How could I modify the content of ROM in sof file without recompiling the whole design?

0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
403 Views

Quartus "smart compile" should help you. 

 

This feature skips compilation stages which aren't needed - in this case it can skip synthesis and routing and just rerun the final stages of compilation. 

 

You can turn it on from the Quartus Assignments/Settings menu - choose "Compilation tools settings" in the tree and then tick the box. 

 

You may find that the "incremental compile" option is useful.
0 Kudos
Altera_Forum
Honored Contributor II
403 Views

Thanks to wombat. Does Quartus provide tools to combain old sof file and new rom hex file to a new sof file?Because the rom content is created by other guy, they don't want to learn vhdl.

0 Kudos
Altera_Forum
Honored Contributor II
403 Views

No. Sorry. 

 

The Quartus II assembler (the stage after routing) needs more information than is available in the SOF file - for example it needs to know which memories your ROM data is initialising etc. 

 

Your other guy doesn't need to know VHDL, they just need to have Quartus installed and be able to check the VHDL out of your version control system and press the start button. Is there a reason why they can't use the "download and debug" flow which the IDE uses? It can usually write to SOPC builder created ROMs.
0 Kudos
Reply