Instantiating on-chip memory in logic

[Altera_Forum]

I am designing a Nios II CPU and trying ot see how much tightly coupled memory I can use. I am using a Cyclone 1C12. I tried 24 KBytes of tightly coupled Instruction memory and 4 KBytes of tightly coupled Data memory. Unfortunately my compiler complained that I didn't have enough M4K blocks to complile the design. Does anyone have any suggestions of a work around ? Is there any way to insatntiate these memory elements directly in logic ?  

 Shmuel

[Altera_Forum]

The 1C12 has 52 M4K memory. Each M4K is 0.5K. The Nios2 core will take 2-4 M4K, more with cached. So you can have only around 20K onchip memory.

[Altera_Forum]

Is there any way to instantiate the tightly coupled memory in logic instead of M4K Blocks ?