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Logic level of output pins at power-up and power-down

Altera_Forum
Honored Contributor II
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Can anybody tell me how to set the logic level of output pins to GND during power-up and power-down? Many thanks.

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Altera_Forum
Honored Contributor II
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Can anybody tell me how to set the logic level of output pins to GND during power-up and power-down? Many thanks. 

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You need to use an external resistor to pull-down the pins you want at logic low level. Altera FPGAs have on-chip weak pull-ups, but not pull-downs. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Thanks.  

 

Unfortunately, I am unable to change anything on my target board.
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Altera_Forum
Honored Contributor II
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No...i have to keep streming the pic to the screen

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