NIOS-FLASH-DRAM

[Altera_Forum]

Hi: 

 I'm trying to get a NIOS running in an Altera Cyclone FPGA. I'm configuring using a epcs (serial eeprom) then booting from FLASH. THe boot process copies a code image from FPASH to SDRAM then jumps to the start in SDRAM.  Running under JTAG is not a problem.  Initially I had RESET* going high before ConfigDone* wnet high. This system would boot OK only if we left power off for 20 seconds or more.  I then linked RESET* to the end of ConfigDone* and this never boots. I also added a delay between RESET* to the NIOS and the NIOS in the fpga. I used the DelayedReset block found in the Cyclone evaluation board design. But that didn't generate any delay. I modified it to work but no different. Never booting.  I've put a logic analyzer on the fpga and see RESET* delayedReset and data being read out of the FLASH.  Has anyone ever got something like this running???  George

[Altera_Forum]

--- Quote Start ---  originally posted by gmm50@Aug 30 2005, 01:29 PM initially i had reset* going high before configdone* wnet high.  this system would boot ok only if we left power off for 20 seconds or more.  i then linked reset* to the end of configdone* and this never boots. i also added a delay between reset* to the nios and the nios in the fpga. i used the delayedreset block found in the cyclone evaluation board design.  but that didn't generate any delay.  i modified it to work but no different.  never booting.  --- Quote End ---   When you say "RESET*" do you mean the DEV_CLRn pin on the FPGA, another pin on the FPGA you're using as a reset, or the reset_n port on the generated SOPC module?  In our designs, I've never needed a special reset pin connection, though sometimes I connected one to a low-voltage detector circuit anyway. The Altera clears all the registers to 0 as part of its initialization sequence after configuration. Read the section in the Cyclone handbook on configuration and initialization for an exhaustive analysis of the whole process.  The delayed reset block (where it holds reset low for a certain amount of time) gives time for things like the PLL to stabilize before coming out of reset; I've also used the "locked" output on PLLs as a reset term.  Recently, I've taken to connecting the nCONFIG pin to the board's RESET net, so that the Altera reconfigures whenever the board is reset. Your mileage may vary.