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NIOS II SPI Slave Issue

n-slipstream
Novice
1,033 Views

I have a MAX 10 FPGA which needs to receive data as an SPI slave.

I have created a Platform Designer project and successfully got all other IP blocks up and running, TJAG UART, NIOS CPU and on chip flash.

 

The issue is this the SPI (3 Wire Serial) core.

It is configured in slave mode with 2 depth synchronizers enabled. I have attached a screenshot of the design. 

 

I have tried polling and interrupts and get similar results. Sometimes the test pattern I send to the SPI slave is received correctly, other times the data is bit shifted by one or is garbage. 

I get similar results to this https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/SPI-Slave-bug/td-p/34282

I have tried the core with 8bit and 32bit data register values, slowed down/increased the input clock and slowed down/increased the external SPI clock.

Does the SPI core clock need to match the NIOS II, I have set 80Mhz .

I noticed the SPI can connect to Avalon data and instruction, is the instruction bus needed it does increase the address range of the block?

The signal quality using an oscilloscope looks good.

 

I have tried a separate approach to use a SPI slave to Avalon master bridge but it has not base address so I'm not sure how the NIOS will communicate to the IP. Is this the right IP to use?

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1 Solution
n-slipstream
Novice
973 Views

I have fixed the issue, the documentation from Intel is incorrect in the Embedded Peripherals IP User Guide page 50+ for MAX 10 Nios II.

https://cdrdv2.intel.com/v1/dl/getContent/732789?fileName=ug_embedded_ip-683130-732789.pdf

 

I simulated the IP in ModelSim and looking at the generated Verilog code there are some comments.

In the Embedded Peripherals IP User Guide it states that the core supports all 4 SPI modes. However in slave mode clock on raising edge is not supported. In master mode all 4 modes are supported.

*Limitation: Only support CPHA=1.

Changing the SPI mode to clock data on falling edge it works fine and without issue, the default configuration in the IP from Platform Designer is to clock on raising edge.

 

@EBERLAZARE_I_Intel 

I have spent a while trying to solve this issue and the documentation should be updated. The documentation mainly covers master mode. Slave only support SPI modes 1 and 3. Also you must enable synchronisers.

sample from /submodules/spiphyslave.v

/************************************************************************** ^M
*Module name: MOSIctl ^M
*Date Created: 15 Nov 2007 ^M
*Last Modified: 15 Nov 2007 ^M
*Description: Transport Bytes downstream from SPI MOSI to avalon ST ^M
*             The SPI Master side consists of:  ^M
              1)  MOSI,nSS,Sclk ^M
*             ST side consists of: ^M
*             2) An Avalon ST source port (ready, valid, data) ^M
*              ^M
*Clock crossing: Clock crossing done using synchronizer and handshaking logic ^M
* ^M
*Limitation: Only support CPHA=1. ^M
* ^M
* MSB/LSB first: MSB first ^M
* ^M
* ^M
*Parameter: BITS_PER_SYMBOL,  ^M
*           SYMBOL_PER_BEAT,  ^M
*           CPOL (Clock Polarity) ^M
*           CPHA (Clock Phase) ^M
* ^M
*Global Define:  ^M
*Internal Parameter:  ^M
* ^M
*CPOL and CPHA description: ^M
* ^M
* CPHA=0: First edge of Sclk is used to capture data, sent at second edge of Sclk ^M
*         This means that first (LSB) byte must be send out from MISO when nSS is low ^M
* CPHA=1: First edge of Sclk is used to send data, second edge of clock capture data ^M
*         (CPHA=1 is used when we need the first edge of Sclk before sending data) ^M
* ^M
* ^M
* Below are data shifting and capturing timing for the 4 different mode for SPI ^M
* ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^M
*    | SPI Mode | CPOL | CPHA | Shift Sclk edge   | Capture Sclk edge | ^M
*    | 0        | 0    | 0    | Falling (negedge) | Rising (posedge)  | ^M
*    | 1        | 0    | 1    | Rising (posedge)  | Falling (negedge) | ^M
*    | 2        | 1    | 0    | Rising (posedge)  | Falling (negedge) | ^M
*    | 3        | 1    | 1    | Falling (negedge) | Rising (posedge)  | ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~          ^M
* ^M
*Note: conditional synthesis is done by using "generate if, end generate"     ^M
*************************************************************************/ ^M
/*simulation resolution*/ ^M

 

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3 Replies
EBERLAZARE_I_Intel
1,008 Views

Hi,


Please allow me sometime to check this issue.


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n-slipstream
Novice
974 Views

I have fixed the issue, the documentation from Intel is incorrect in the Embedded Peripherals IP User Guide page 50+ for MAX 10 Nios II.

https://cdrdv2.intel.com/v1/dl/getContent/732789?fileName=ug_embedded_ip-683130-732789.pdf

 

I simulated the IP in ModelSim and looking at the generated Verilog code there are some comments.

In the Embedded Peripherals IP User Guide it states that the core supports all 4 SPI modes. However in slave mode clock on raising edge is not supported. In master mode all 4 modes are supported.

*Limitation: Only support CPHA=1.

Changing the SPI mode to clock data on falling edge it works fine and without issue, the default configuration in the IP from Platform Designer is to clock on raising edge.

 

@EBERLAZARE_I_Intel 

I have spent a while trying to solve this issue and the documentation should be updated. The documentation mainly covers master mode. Slave only support SPI modes 1 and 3. Also you must enable synchronisers.

sample from /submodules/spiphyslave.v

/************************************************************************** ^M
*Module name: MOSIctl ^M
*Date Created: 15 Nov 2007 ^M
*Last Modified: 15 Nov 2007 ^M
*Description: Transport Bytes downstream from SPI MOSI to avalon ST ^M
*             The SPI Master side consists of:  ^M
              1)  MOSI,nSS,Sclk ^M
*             ST side consists of: ^M
*             2) An Avalon ST source port (ready, valid, data) ^M
*              ^M
*Clock crossing: Clock crossing done using synchronizer and handshaking logic ^M
* ^M
*Limitation: Only support CPHA=1. ^M
* ^M
* MSB/LSB first: MSB first ^M
* ^M
* ^M
*Parameter: BITS_PER_SYMBOL,  ^M
*           SYMBOL_PER_BEAT,  ^M
*           CPOL (Clock Polarity) ^M
*           CPHA (Clock Phase) ^M
* ^M
*Global Define:  ^M
*Internal Parameter:  ^M
* ^M
*CPOL and CPHA description: ^M
* ^M
* CPHA=0: First edge of Sclk is used to capture data, sent at second edge of Sclk ^M
*         This means that first (LSB) byte must be send out from MISO when nSS is low ^M
* CPHA=1: First edge of Sclk is used to send data, second edge of clock capture data ^M
*         (CPHA=1 is used when we need the first edge of Sclk before sending data) ^M
* ^M
* ^M
* Below are data shifting and capturing timing for the 4 different mode for SPI ^M
* ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^M
*    | SPI Mode | CPOL | CPHA | Shift Sclk edge   | Capture Sclk edge | ^M
*    | 0        | 0    | 0    | Falling (negedge) | Rising (posedge)  | ^M
*    | 1        | 0    | 1    | Rising (posedge)  | Falling (negedge) | ^M
*    | 2        | 1    | 0    | Rising (posedge)  | Falling (negedge) | ^M
*    | 3        | 1    | 1    | Falling (negedge) | Rising (posedge)  | ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~          ^M
* ^M
*Note: conditional synthesis is done by using "generate if, end generate"     ^M
*************************************************************************/ ^M
/*simulation resolution*/ ^M

 

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EBERLAZARE_I_Intel
960 Views

Hi,


Thanks for your feedback, I shall channel the feedback to our internal team.


If you have further questions, you may open another ticket.


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