NIOS II booting problem from EPCS, not sure on Reset Vector Offset

[Ganesh]

Hi all,

I know that there are many posts on the same topic, but no post helped me in solving my issue. 

I am having problem booting up my Nios C code from EPCS. I have NIOS II Faster Processor in my desing and using with Quartus 11.0 (also tried with Quartus 14.1) and Cyclone IV E as FPGA.
I have IPS-Embedded license bundle. In hardware I have 64Mb Serial Flash Device (EPCS64)
In logic I have instantiated
1. Nios II Faster Processor: Its Reset Vector is pointing to base address of EPCS Controller(0x1008_0000) with offset to 0x0000_0000. Exception vector to OCM base address(0x0002_0020) with offset to 0x0000_0020 (this offset is automatically generated).

2. EPCS Serial Flash Controller: This core is instantiated at base address 0x1008_0000.

3. PIO : in order to control LED operation. This core is instantiated at base address 0x0004_2020.

4. UART RS232 Serial Port: Instantiated at base address 0x0004_2000 for UART data transfter.

There is no external reset pin, the JTAG debug module reset out is connected to all reset inputs.

For the test purpose, I have a while loop in NIOS II application in which some prints are send to console and LED is blinked. LED is active low.

I generate .jic file using following steps:
1. First I generate Flash files using following commands
   sof2flash --epcs --input="fpga.sof" --output="FPGA.flash"
   elf2flash --epcs --after="FPGA.flash" --input="test.elf" --output="fpga_sw.flash"
  
2. I gerenerate .hex files as follows
   nios2-elf-objcopy -I srec -O ihex fpga.flash  fpga.hex
   nios2-elf-objcopy -I srec -O ihex fpga_sw.flash  sw.hex
  
3. Then Using Convert Programming Files in Quartus, I create a JIC file using the steps below:
   a) Select EPCS64 (that is the flash chip i'm using)
   b) Add flash loader as EP4CE40 (Cyclone IV E FPGA I am using)
   c) Add sw.hex file with absolute address and start address is automatically given 0x0006_4E5F.
   d) Add fpga.hex file with absolute address and start address is automatically given 0x0000_0000.
   e) Then Generate .jic successfully
  
4. Then I flash this file on to the flash memory using USB-Blaster. Everything is fine till here.

But after restart I see that only FPGA Boots (LED is on), but NIOS does not (No prints on console and no LED blinks)

 
To test the working of desing and hardware, I changed NIOS II Reset vector to OCM and generated .sof file in quartus and .qip file in Eclipse using mem_init and then I included this qip file in the quartus project
and there after regenerated .sof file. When I load this .sof file directly on to OCM everything works just fine. I can see some prints are coming on console and LED is blinking.
 
Any ideas what is going wrong?

I am not sure about Reset vector and Exception vector offset values.
In some forum posts I have seen some people changed offset values and then it worked for them. But what should be the value of offset?

 
Thanks in advance 
 
 
Best regards

[EricMunYew_C_Intel]

Hi, Ganesh

May I know you intend to run your application directly from the flash ? or you intend to copy your application from flash to RAM and run from RAM ? do you have external RAM ?

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Ganesh

You can refer to page 254 of below for reference.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf

It will demonstrate how Nios booting from EPCQ (or EPCS). The application can be copied to OCRAM using a boot copier.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Ganesh

Can I close this if you have no more inquiry ?

Thanks.

Eric