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Hi all,
I am a NIOS and overall beginner at all things Altera. I have recently been trying to build a project in qsys (shown in the picture)to run on my De0-Nanohttps://www.alteraforum.com/forum/attachment.php?attachmentid=8364 . When i program the hardware it goes smoothly. I generate the qsys and use it as the basis of a .bdf file as the top level where i define all the pins and the programming is successful. When i open the NIOS IDE, i make a new hello world project from the templates with BSP file. I generate the BSP, build the BSP file, build main project file, run as nios hardware. I get 1 of a couple of errors: 1)https://www.alteraforum.com/forum/attachment.php?attachmentid=8365 2)https://www.alteraforum.com/forum/attachment.php?attachmentid=8366 https://www.alteraforum.com/forum/attachment.php?attachmentid=8367 I have tried multiple times to start over and recompile everything, but these errors persist. Thanks in advance. I am using quartus 13.0 and nios 13.13.Link Copied
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How is the reset connected to the clocksys from your toplevel? And is your clock connected on toplevel and in the PIN-Assigments?
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The reset is output to another name and then assigned to Pin J15 (Key0 on the De0-Nano).
The clock is output to another name and then assigned to Pin R8 (CLK_50 on the De0-Nano). On the qsys symbol, both are input pins tied to VCC. Thanks for the reply.
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