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NIOS core on DE2 (cyclone II)

Altera_Forum
Honored Contributor II
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I have access to DE2 boards and am interested in putting the NIOS core onto it with simple sockets communicating to a server on a PC. 

 

I was wondering if anyone knows roughly how much leftover logic on the FPGA there would be to implement something like custom instructions for the NIOS? I've been told by my classmates that the NIOS core consumes almost all of the resources of the DE2's cyclone II chip.  

 

I'm really only looking for a rough answer. (ie lots of leftover logic cells or very few...)
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Altera_Forum
Honored Contributor II
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It probably depends on how many of the optional features you have in the nios itself. 

Remove features you don't need, cut down the size of the JTAG debug to minimum (etc) and it will free up resources. 

Simple custom instructions won't use much logic.
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