NIOSV EIC , MPU and MMU ip cores - availability plan & date?

[monkstein]

Hi there Intel, 

I recently started using the NIOSV cpu on my Terasic DE0-NANO board (featuring Cyclone IV fpga),  and just tried to create some example projects to just tinker with and experiment with this new CPU core.  (Using Quartus 23.1.1 Standard on Win.)

https://github.com/monkstein88/niosv-example-projects

I recently wanted to implement (add) in the QSYS design a Vector Interrupt Controller and either an MPU (Memory Protection Unit) or MMU (Memory Management Unit) . But I noticed that :

1. It seems that neither of the NIOSV CPU versions supports/features external interrupt controller (EIC) capabilities. Which impacts interrupt handling performance.

2. Neither MPU nor MMU features are available for any type of NIOSV, which blocks the ability to run any bigger OS i.e. Linux on this cpu core.

So, in my opinion, at the moment, it seems the NIOSV core is somewhat limited in its capabilities.

But  I just want to ask if you plan and if so when, to include the EIC , MMU and MPU features for  the NIOSV? 

Thank you,

M.M. 

[JingyangTeh · Accepted solution]

Hi

The the EIC, MOU and MMU for the NiosV are planned to be available on the timeframe of 2025/2026. They have not finalized the date yet.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Do you have any follow up question for this case?

Regards

Jingyang, Teh

[monkstein]

Hi,

I just wish those features came sooner  

BR,

- M.M.

[JingyangTeh]

Hi

Sorry about the inconvenience caused.

Due to the engineering planning they have plan for it to be that time frame.

I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh