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Dear all,
We are preparing one design for Arria 10 GX Development kit. That design is having following components:- Nios II (Gen2) Processor with MMU enabled
- DDR4 memory.
- On-chip memory as a reset vector (offset 0x0), exception vector (offset 0x20) and fast TLB miss exception vector (offset 0x100).
- JTAG UART alongwith interval timer are also there in design. As suggested at http://www.alterawiki.com/wiki/uclinux#let.27s_start_it_step_by_step in Altera wiki, interval timer has been assigned IRQ0 and JTAG UART IRQ1.
- We have ensured that total address span does not exceed 512MB. (Not sure why do we need this limitation?)
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Hello,
First of all thanks to those who read my post and tried to see whether they can help or not. At last, we were able to get past that issue. I am sharing how we solved it here. Hope this could be helpful to someone in future.- We ensured that all peripherals (including memories) connected to Nios II's instruction master and data master are within address range: 0x0 to 0x1FFFF_FFFF. (Not very sure why we need to ensure this.)
- We made following manual changes in DTS file generated from .sopcinfo
- DDR4 memory is not located under memory section. Hence we manually edited it under memory section and comment it out from other section.
- Under CPU section, 'altr' needs to be replaced with 'ALTR'. It seems that to use Nios II gen2 processor with Linux kernel version 3.4, this change is required. (I read this somewhere on Rocketboards.org)

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