Problem with asynchronous reset and booting

[Altera_Forum]

Hello 

I have the NIOS configured to boot the boot from the on-chip memory. The first time successful startup. When you reset the NIOS using asynchronous reset signal the BOOT not load a software. Using the In-System Memory Content can be seen that the memory content is corrupted.  Is there any way around this?  Used the quartus 13 sp1.  thanks

[Altera_Forum]

Is the on-chip memory a RAM or a ROM If it is a RAM it is possible that your software modifies it when running, making it unbootable afterwards.

[Altera_Forum]

If i configure the on-chip memory as ROM the NIOS not init never, 

Is it possible to configure the BIOS to boot from an external ROM BOOT instead of using the on-chip memory? How to be configured? Regard

[Altera_Forum]

You will need both a ROM and a RAM. A ROM to hold the software, and a RAM to hold the exception vectors and all the variable sections (data and bss, mostly). Remember in the Nios CPU configuration to set the reset vector to your ROM and the exception address to your RAM. 

There isn't any BIOS but yes you can configure your system to boot from an external rom. If it is a parallel ROM, then you just have to set the Nios's CPU reset vector to this ROM. If it is an EPCS, then set the CPU's reset vector to the EPCS controller address. The controller has a small ROM that contains a bootloader able to load a software image from the EPCS and recopy it to RAM.

[Altera_Forum]

It seems the data section of your program in RAM is overwritten and it will cause the subsequent run won't work. 

By having say so, you can work it out by choosing either below solution  1. Always getting the boot copier copy the program from flash and store at the RAM. By doing that, the data section is always new 2. This is little bit advanced. You can duplicate your data section in the linker. One of them would change during the program run but another one would be static. When your program run (in assembly), always overwrite the data section with the static one. This would ensure the data section is always new. This is little advanced but would save the flash accessing time.

[Altera_Forum]

I was on vacation.I could not answer 

 I discuss more thoroughly the project. The QSYS is composed of: -> Ddr2 (Altera DDR2 controller). -> EPCS with HW and SW. -> On-chip Memory with BOOT.  The EPCS contains 2 versions of HW and SW for both. The idea is that the boot start the SW of the EPCS. Analyzing the In System Memory Content Editor the EPCS contains the correct BOOT at first, but after starting the SW its content changes. Few bytes are changed. Because of this after the reset the NIOS will not start. If from the In System Memory Content I restored the original BOOT and I effort reset the NIOS starts.  Also I tried during SW debugging the content changes before reaching the main ().  The BSP configuration editor is the picture 1.   The configuration of the on-chip memory is the picture 2.     Image 3 is the comparison of on-chip memory before and after start of SW.

[Altera_Forum]

What code do you have in this BOOT memory? If it changes, then it means that at some point your software writes to this section. If you enable the CPU with hardware breakpoints, I think you can make it stop when it tries to write something to that location. (I've never tried this though, so I can't help you set it up)

[Altera_Forum]

It is my bootloader. 

The SW is in 0x60000 in a epcs flash.

[Altera_Forum]

Its an error in Quartus. 

http://www.altera.com/support/kdb/solutions/rd05262013_431.html?gsa_pos=3&wt.oss_r=1&wt.oss=on-chip%20ram%20and%20rom