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12618 Discussions

Programming FPGA from HPS using QSPI

Honored Contributor II



I have a de1-soc I am trying to program the fpga from the qspi connected to the hps At this time I was able to load the preloader, run a bare metal application on the arm, but when I try to load the fpga me from timeout error. I edited the socfpga_common.h preloader file, defined as the CONFIG_SPL_FPGA_LOAD variable, and inserted the correct address in CONFIG_SPL_FPGA_QSPI_ADDR. The FPGA firmware is in rbf format generated by soc eds. When i start preloader i get this: 


U-Boot SPL 2013.01.01 (Jun 06 2017 - 13:01:59) 

BOARD : Altera SOCFPGA Cyclone V Board 

CLOCK: EOSC1 clock 25000 KHz 

CLOCK: EOSC2 clock 25000 KHz 

CLOCK: F2S_SDR_REF clock 0 KHz 

CLOCK: F2S_PER_REF clock 0 KHz 

CLOCK: MPU clock 925 MHz 

CLOCK: DDR clock 400 MHz 

CLOCK: UART clock 100000 KHz 

CLOCK: MMC clock 50000 KHz 

CLOCK: QSPI clock 370000 KHz 


SDRAM: Initializing MMR registers 

SDRAM: Calibrating PHY 

SEQ.C: Preparing to start memory calibration 


SDRAM: 1024 MiB 

FPGA : Programming FPGA 

SF: Read data capture delay calibrated to 3 (0 - 6) 

SF: Detected S25FL512S with page size 65536, total: 67108864 

FPGA: Poll CD failed with error code -4# ## ERROR# ## Please RESET the board# ## 




Can someone help me? 


Thank you
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3 Replies
Honored Contributor II

I found the error. 

The error is in the preloader when try to transfer the fpga file. 

Looking into the preloader in the file spl.c there is this function: 


void spl_program_fpga_qspi(void) 

struct spi_flash *flash; 

struct image_header header; 

u32 flash_addr, status, transfer_size; 

u32 temp[64]; 





while (spl_image.size) { 


* Read the data by small chunk by chunk. At this stage, 

* use the temp as temporary buffer. 


if (spl_image.size > sizeof(temp)) 

transfer_size = sizeof(temp); 


transfer_size = spl_image.size; 


spi_flash_read(flash, flash_addr, transfer_size, temp); 

/* update the counter */ 

spl_image.size -= transfer_size; 

flash_addr += transfer_size; 


/* transfer data to FPGA Manager */ 

fpgamgr_program_write((const long unsigned int *)temp, 

transfer_size);# ifdef CONFIG_HW_WATCHDOG 





when I read the value of the spl_image.size it was half of the full dimension of my rbf program. 

I tryed to modify this value by manually writing spl_image.size to the correct value and finally the fpga works. 


Now I think that the problem is the header of the .rbf file. 

How can I modify the header file?
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I have a custom board with cyclone V SOC . I have a 1Gbit QSPI flash attached to the HPS portion of SOC. I want to boot the HPS with qspi flash. I able to do it debug mode. But not able to do it in program mode. what i mean is that i am able to load the rbf files into the qspi flash and read back this files and program the fpga successfully in debug mode. But when i try to do it program mode it is not working. I have generated preloader_-mkpimage.bin file with all the necesssary settings as mentioned in HPS qspi boot guide documentation. i load this preloader-mkpimage in 0x00000000 address of QSPI flash using the commands in SOC Command shell. then i load my application bin file generated after compilation of my design at 0x60000 address of flash by using commands in SOC EDS Command shell. Both this operation is successfull. MSEL pins are correctly selected for QSPI Boot. When i reboot the equipment the system is not booting. Am i missing certain settings at bsp generation or in make file or the linker file. Please specify.





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Hello if you are able to boot from QSPI in debug mode. then before programming you qspi flash make then remove all printf code from your code. and make the image without print lines. it will be possible to boot using this image file. 



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