Qsys with up to 8 GB of DDR2

[Altera_Forum]

Hi all, 

 Im developing an application that requires more than 1G DDR2 memory, but I cant use it direct on Qsys because Avalon address is restricted to n^31. I'm developing on Stratix IV FPGA (Terasic DE4).  I would like to know with any of you have already face this problem and how can I handle this on the best way.  Best regards,  Rafael C.

[Altera_Forum]

Although I haven't done this on the Stratix 4 board yet (haven't needed that much memory yet), you can use the AXI bus in QSYS and get up to a 64 bit address space. 

 I have used AXI with the Cyclone V SOC kit, and with the Xilinx Zync platform, and it's a powerful bus interface. The Problem is this doesn't seem to be supported by NIOS II yet. (Only 32 bit CPU, so it's tough to address > 4 GB)  The best solution I guess is dependent on your real requirements. If you need it for code space you can do blocks of memory, but it's a pain to manage. If you need it for physical data space for the rest of the hardware, you can create a custome interface, that gives avalon access to 2GB, and the hardware the the rest of your FPGA hardware the rest.  Pete