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Questions about programming the NIOS CPU

Altera_Forum
Honored Contributor II
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I'm not sure if this should be in this forum, or in the general forum, but I'll put it here, since most of my questions are software related. 

 

Some background on my project: 

This is being done for a 4th year design project in Electrical Engineering, and this is my first experience with any kind of high end (mor ethan 8051) embedded system programming. I'm using a Stratix Professional Edition (Stratix 1S40 FPGA) dev kit, with Quartus II Version 4.0 and NIOS version 3.10 (that's the versions of the software that my supervisor had available, unfortunately I can't use the newer version of NIOS with this version of Quartus II). 

 

The project involves sending streaming video over Ethernet. Fortunately, I don't have to do any of the video processing on chip, all that I am doing is processing data that is coming out of a compression chip. So, I have a 32-bit parallel (I was thinking I would probably use one of the Proto2 40 pin busses) that will continuously be sending me data, and I must forward that data to the other development board over TCP/IP on Ethernet, which then sends it back out in real time to the decompression ASIC. 

 

My problem is that I'm not sure what the best way to approach this would be. I was thinking I should take the incoming data and buffer it in memory, then send it out (not sure if I should do this in DMA or let the CPU handle it all in software. Will I run into performance issues if I do it in software? I am likely going to need ~30Mbit/second of throughput on the ethernet port). How exactly should I handle the buffering, and how do I create a circular style buffer that over-writes itself with new data (once that data has been transmitted (and TCP ACK received, something that plugs handles for me) it can be deleted). Can I create the kind of buffer that I want by using the DMA features? 

 

I'm currently at the point that I've gone through all the included NIOS tutorials, and I've made the example PLUGS programs run, as well as modifying them slightly, but I'm not sure where to proceed from here. I've begun to write the program I need to use on the receiver side, but I'm stuck with this whole buffering issue. 

 

Sorry if these are bad questions to be asking, if there are some ressources that I&#39;ve missed reading about it, please let me know. Any help I can get will be much appreciated http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif .
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Altera_Forum
Honored Contributor II
372 Views

As a general rule, you should update your tool set to the latest ones. You should move to the latest quartus2 5.1 sp1, Nios2 5.1 sp1. You can download them from Altera. 

 

You should read all the docs of Nios2 hard/soft/peripheral and avalon bus spec. 

 

The data rate is quite high for a 100M ethernet. It is very tight. You have to be very careful in both hardware and software design. You have to use DMA (with FIFO) to do the data in/out. Even crc32 of packet is very crititcal. 

 

It is not easy as it seems to be. You have to learn and work very hard. Good luck.
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Altera_Forum
Honored Contributor II
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Are you sure that I can download the new versions from Altera? I saw that I can download the web editions of both pieces of software, but I didn&#39;t see the full versions anywhere. I was using Quartus II 5.1 Web Edition, along with NIOS II Version 5.0 (from a disk), but then I discovered that the web edition doesn&#39;t support my particular FPGA, so I had to switch to using the older versions of the software.

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Altera_Forum
Honored Contributor II
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It seems you have the Quartus key. 

You should ask for Quartus subscription update from Altera. 

Always use the latest tools!
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Altera_Forum
Honored Contributor II
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I&#39;m actually doing something similar. Buffering video in the FPGA and then passing off a frame of video over ethernet for display on another machine.  

 

What I&#39;m working on now is a seperate component (VHDL) that buffers and fifos the incoming data and will probablt drop it into memory and then send an IRQ. From there SW can packetize the data into UDP packets and send them out.... 

 

 

For these speeds i think the more you can do without software intervention, the better...
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