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RAM -> DMA -> UART, How to set up?

Honored Contributor II


My requirement is to be able to fill an area of RAM with a message c. 512 bytes and then use DMA to transfer that 512 bytes into the UART. From what I can glean the UART / DMA interface will automatically handle the flow control. I am a little unsure as to how the NIOS should connect to the UART. Obviously the NIOS needs to connect to the RAM to fill it with data. I have used dual port ram and port# 2 connects to the DMA read port. The DMA write port connects to the UART. After filling the RAM I intend to start a 512 byte transfer with a constant write address. Does the NIOS connect to the UART or is that unnecessary? 



The return message will vary in size but I know the maximum number of bytes that could possibly be received. Can I set up the system such that the DMA is setup for the maximum message length and periodically check the number of bytes received? 


Finally how does the DMA work for full duplex with the UART? Do I need to use 2 DMAs? 


Many thanks
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Honored Contributor II

I am close to believing there is a real problem here. 


Altera documentation "Embedded Peripherals IP User Guide" (UG-01085 2015.12.16) states:- 


"The DMA controller transfers data as efficiently as possible, reading and writing data at the maximum 

pace allowed by the source or destination. The DMA controller is capable of performing Avalon transfers 

with flow control, enabling it to automatically transfer data to or from a slow peripheral with flow control 

(for example, UART), at the maximum pace allowed by the peripheral." 



The Avalon-MM slave port is capable of transfers with flow control. The UART core can be used in 

conjunction with a direct memory access (DMA) peripheral with Avalon-MM flow control to automate 

continuous data transfers between, for example, the UART core and memory. 


The signal to stall the Avalon Master from the Slave is "waitrequest". The UART outputs "readyfordata". These signals are not connected by QSYS! 


Connecting them in the QSYS generate code (with inversion) makes DMA->UART partly work. But it skips bytes. Perhaps "readyfordata" does not work as "waitrequest_n" should. 


Any thoughts? 


I am thinking the documentation might be wrong ? . . .
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