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Read access through Avalon-MM tristate bridge

Altera_Forum
Honored Contributor II
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Hi there, 

 

I was simulating an external memory access through Avalon-MM tristate bridge and the data width of my external memory is 16 bits. Everything worked fine except that, it always performs two read cycles for 8bit or 16bit reads, with all byte enables disabled in one of the read cycles. This practically reduced the bandwidth in half on the memory interface for read access. 

 

My question is, is this fixed in SOPC builder for the versions later than QII 9.1 SP2? 

 

Thanks, 

Hua
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Altera_Forum
Honored Contributor II
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I'm pretty sure this is a known issue. I don't expect it to be fixed and that users who want to avoid this should use Qsys instead.

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Altera_Forum
Honored Contributor II
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As BadOmen said, this is indeed a known issue which was discussed elsewhere in the forum. 

If you use the external memory only for 16bit data, you can define the tristate data port 32bit wide and discard the upper 16bits. This will ensure a single access for every read operation.
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Altera_Forum
Honored Contributor II
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As well as behaviour of the bus width adapter (which might do cycles with no asserted byte enables), the nios2 processor always asserts all 4 byte enables for its memory reads - regardless of the requested width.

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