Reading rooport's PCIe HIP configuration space

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Reading rooport's PCIe HIP configuration space

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Hi!

I have a PCIe system based on Cyclon V GX Terasic DE1 (rootport) and Altera Cyclone V GT (endpoint) development boards.

On the rootport side I connected Avalon-JTAG master to CRA and TXS Avalon slave ports of the HIP.

1. How can I access the Configuration Space of RootPort PCIe HIP - should I use the CRA avalon port for this (and what is the way if so...)?

2. What is the sequence of operations on Avalon Bus to read Configuration Space of RootPort?.... EndPoint?

3. As much as I understood from Altera doc's I can send the all type of TLP's through Root Port TLP Data Registers on CRA avalon port.

It's not clear - what the Avalon TX slave port is for?

Thanks in advance!

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