Remote system upgrade for MAX 10 with Cypress quad SPI Flash

[PRibe4]

I'm working on configuring a remote system upgrade (AN 741) with a dual image configuration using an external SPI flash to store the NIOS 2 hex (Boot option 5 from chapter 1.5.3.2 from AN 730).

Currently I'm using a custom board that has a MAX 10 FPGA and a Cypress Flash S25FS512S.

I've tested the Intel FPGA Generic quad SPI controler core II with the MT25QL512ABA Flash selected and I'm able to get the correct Flash silicon ID but read and write operations don't seem to work correctly.

Here is an example where the program writes 0xbb in memory but always reads 0xcc.

I'm able to read the correct SPI flash ID with (IORD_ALTERA_QSPI_CONTROLLER2_RDID) but It seems like the values are not being written in Flash.

memset(source, 0xbb, BUF_SIZE);   fd = alt_flash_open_dev("/dev/generic_quad_spi_controller2_0_avl_mem"); if (fd!=NULL) { ret_code = alt_qspi_controller2_get_info(fd, &regions, &number_of_regions); if(ret_code==0){ alt_printf("len %x \n",fd->length); alt_printf("regions %x \n",number_of_regions); alt_printf("string %s \n",fd->name); }   silicon_id = IORD_ALTERA_QSPI_CONTROLLER2_RDID(GENERIC_QUAD_SPI_CONTROLLER2_0_AVL_CSR_BASE);   alt_printf(" %x \n",silicon_id); ret_code = alt_qspi_controller2_write(fd, 0, source, BUF_SIZE); //writes 0xbbb    ret_code =alt_qspi_controller2_read(fd, 0, source2,BUF_SIZE); //always reads 0xccccc   if(ret_code==0){   alt_printf("source %x \n",source[0]); alt_printf("source 2 %x \n",source2[0]); }   alt_flash_close_dev(fd);   }

As an alternative I've also tested the Generic Serial Flash interface IP core. Using this one I'm able to successfully run the reference design (UG-20161) code and read and write from the SPI Flash so I know Its not an hardware problem.

However I'm not able to generate the BSP for NIOS 2 with this IP core due to no matching memory region errors and so I can't boot from It.

SEVERE: CPU "RSU" reset memory "intel_generic_serial_flash_interface_top_0_avl_mem" has no matching memory region.

SEVERE: CPU "RSU" reset memory "intel_generic_serial_flash_interface_top_0_avl_mem" has no matching memory region.

SEVERE: nios2-bsp-generate-files failed.

This problem is similar to the one that another Forum user was having:

https://forums.intel.com/s/question/0D70P000005PLF2SAO

Is there a solution for this?

I'm using Quartus prime standard edition 18.0.

[Ahmed_H_Intel1]

Hi, Do you able to run the MEM-test project on this board, please make sure the mem-test passes with the flash device. Mainly I still suspecting the "Generic Quad SPI IP" parameters. please review the flash datasheet and run the mem-test before testing your design. Regards,

[PRibe4]

Hello, thank you for the reply.

I ran the memory-test project and it seems to stop after checking for erased blocks...

/dev/generic_quad_spi_controller2_0_avl_mem -Successfully opened /dev/generic_quad_spi_controller2_0_avl_mem -Region 0 contains 1024 blocks. -Checking Region 0 for erased blocks.   Press enter to continue...

I took a closer look at the datasheets from MT25QL512ABA and S25FS512S and there seems to be a diference in the sector sizes and dummy cycles mismatch.

How can I edit these parameters in the Generic quad SPI controler core II ?

[Ahmed_H_Intel1]

Hi Pedro,

Are you clearing the NIOS II cash? this makes you unable to see what is written easily.

Can you please share with me your system blocks?

Please check the following link for useful examples:

https://fpgacloud.intel.com/devstore/platform/?acds_version=any&ip_core=Flash&family=max-10&category=2

Regards,

[PRibe4]

Hello,

After emailing support I reached a conclusion that the Cypress S25FS512S is not compatible with the Generic quad SPI controler core II IP.

They suggested using the Generic Serial Flash interface IP instead to boot from on-chip-ram and then write my own boot copier to copy the data from flash to ram then switch.

As a quick alternative I switched the flash to a Micron MT25QU512ABB and it worked!

I'm now able to successfully read, write and boot from the external quad SPI flash.

Thank you for your Assistance

Best Regards

[Ahmed_H_Intel1]

Thanks Pedro for your confirmation.

This is a helpful design example for using serial flash device. you can download it and know how to use this IP.

https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/

Regards,

[Muhammad_Ahsan_Razaq]

Hello @Ahmed_H_Intel1,

I am using the Generic Serial Flash Interface intel FPGA IP with Cyclone V E FPGA and Micron MT25QL256.

While using NIOS II Flash programmer GUI, I get Error code 4 for nios2-flash-programmer when I add .elf and .sof file, and try to burn it in FLASH.

Also, I tried using Prime Programmer.

I combined and convert .sof and .elf to .hex using command line and finally to .jic file using Convert Programming File GUI.  My program didn't get properly burned in flash.

I want to have both hardware and software in flash.

Other issue that I am facing is, when I use intel_generic_serial_flash_interface and put reset vector of NIOS II to intel_generic serial flash memory. I get the following error when generating BSP file.

Error executing 'nios2-bsp-generate-files --bsp-dir . --settings settings.bsp', unexpected return code 1.

Error message:

SEVERE: CPU "nios" reset memory "intel_generic_serial_flash_interface_top_0_avl_mem" has no matching memory region.
SEVERE: CPU "nios" reset memory "intel_generic_serial_flash_interface_top_0_avl_mem" has no matching memory region.
SEVERE: nios2-bsp-generate-files failed.

If you could please answer the above mentioned queries.

Regards,

Ahsan