Nios® V/II Embedded Design Suite (EDS)
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Run as Hardware

Altera_Forum
Honored Contributor II
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What is the details about the "Run as Hardware"?  

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1. What is the "Controller logic" or "boot loader" in NiosII side, especilly the JTAG UART?  

2. How does it receive data from JTAG cable to volatile memory, such as SRAM or On-chip memory or SDRAM, and then run from the volatile memory?
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Altera_Forum
Honored Contributor II
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When you select "Run as hardware" from the IDE it does the following: 

1) downloads the code to the target using nios2-download. This will set up your uninitialised memory. nios2-download then starts the processor at the entry point specified in the ELF file. 

2) starts nios2-terminal to listen on the JTAG UART or UART specified. 

 

There is no boot loader on the target (Nios II) side in this case - the download is all done by the JTAG debug core built in to the processor.  

 

nios2-download talks to the JTAG debug core, nios2-terminal talks to the JTAG UART. They are separate command line applications which are pulled together by the IDE.
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Altera_Forum
Honored Contributor II
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Hi,wombat 

 

How can the JTAG Debug Core download the code into kinds of momery?? 

Are there extra options during this process?  

If try to download the code to a external SSRAM, are there any extra works??
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Altera_Forum
Honored Contributor II
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The JTAG debug core uses the processors data master to write to memory, so anything which is accessible from that master can be written. In addition, some on-chip ROMs are writable when the processor is in debug mode. 

 

The options available are displayed if you type `nios2-download --help`.
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