SLAVE read with variable latency problem

Nios® V/II Embedded Design Suite (EDS)

Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

SLAVE read with variable latency problem

1,049 Views

Hi All,

I wrapped a slave module with variable read latency in SOPC (Quartus 4.2).

I set in the .ptf :

1) Read_Latency = 0

2) Maximum_Pending_Read_Transaction=16

3) Read_Wait_State="peripheral_controlled"

4) also my slave module has a readdatavalid pin

All my masters are latancy aware. The generated switch produce a readdatavalid signal at the master that is wrong. It seems to be related only to the read and wait signal of my master. It looks like the latency is fixed to 0. Is there an other keyword for the .ptf I should add in order to tell SOPC that my slave module has a variable read latency capability?

Regards,

Alain Marchand

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.