Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12690 Discussions

Simulating NIOS2 core in modelsim(newbie question)

Altera_Forum
Honored Contributor II
1,497 Views

Hi there, 

 

I just got NIOS2 and I am trying to get a simulation of the standard example working in Modelsim. When I try to run the simulation I get this message: 

# ************************************************************# This testbench includes an SOPC Builder Generated Altera model:# 'sdram_test_component.vhd', to simulate accesses to SDRAM.# Initial contents are loaded from the file: 'sdram.dat'.# ************************************************************# ** Fatal: (vsim-3710) Qualified expression type mark slv4 constraint 1 to 4 is not same as operand constraint 5 to 8.# Time: 63 ns Iteration: 1 Process: /test_bench/dut/the_cpu/nll0ioii/line__768 File: C:/altera/kits/full/cpu_test_bench.vhd# Fatal error at C:/altera/kits/full/altera_vhdl_support.vhd line 451 

 

the code it is refering to is automaticly generated and as far as I can see just tries to get rid of the zeros. All I did was generate a standard CPU with modelsim support from the standard example, start NIOS2 IDE, make a hello world project, run it as modelsim program. In modelsim it automaticly sets up and I just use the s and w commands to start the simulation, but when I run it it gives me the error above after 60ns.  

I followed this document http://www.altera.com/literature/an/an351.pdf (http://www.altera.com/literature/an/an351.pdf)  

I used only premade things, so why is it going wrong? 

Hope you have an answer. 

 

Regards, 

David 

 

BTW, I am using Quartus II 4.1 and Modelsim SE PLUS 6.0a
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
375 Views

Hi, 

 

Modelsim 6.0 and beyond is stricter in its interpretation of the VHDL LRM. The stricter interpretation exposes this issue. The quick work around is to replace slv4'(... with slv4(... and slv3'(... with slv3(... in the altera_vhdl_support.vhd file. (i.e. get rid of the ' ) 

 

For those that are interested the rule that is causing problems is: 

 

"The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark." 

 

For an array object, "belongs to the subtype" means that the index bounds must match those of the subtype (not just the length of the array). 

 

 

This rule was not enforced in the previous versions of Modelsim. The latest version of SOPC builder (Version 4.2) has dealt with this.  

 

 

Sean
0 Kudos
Altera_Forum
Honored Contributor II
375 Views

Thanks a lot Sean. The workaround works. 

Both the altera and modelsim support people just told me I had to upgrade to fix the problem....
0 Kudos
Reply