Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.
12583 Discussions

TCP/IP via TSE and Marvell PHY

Altera_Forum
Honored Contributor II
2,796 Views

Hello, 

 

I have the Nios II dev board Stratix II edition. In addition, we have the MoreThanIP Marvell 10/100/1000 Ethernet daughter card that can be stuck on the dev board. I'm looking for documentation and/or reference designs for implementing the complete TPC/IP stack with this setup. The software side probably is the simplest, because Altera provide Nios II drivers for the TSE. However, how to build the system in SOPC and connect TSE to the PHY? 

 

The Altera reference design for ethernet uses a GX board with direct connection from the FPGA to the SFPs, and MoreThanIP's ref designs include *their* MAC and not Altera's TSE. Both aren't what I'm looking for. 

 

Thanks in advance
0 Kudos
15 Replies
Altera_Forum
Honored Contributor II
581 Views

What is the PHY chip on the board and what interface does it use? If you have a look at the TSE datasheet it will detail every possible interface and how it must be connected.

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

 

--- Quote Start ---  

What is the PHY chip on the board and what interface does it use? If you have a look at the TSE datasheet it will detail every possible interface and how it must be connected. 

--- Quote End ---  

 

 

Marvell PHY 88E1111
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

Then you probably have a GMII or RGMII interface between the PHY and the MAC. The schematics from the daughter card should help you find out wich one. The GMII interface uses 8 bits in each direction, whereas the RGMII uses 4.

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

can you please answer this simple question Marvel Alaska 88e1111 is software programmable? or hardware programmable only by changing low high states on its pin?

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

Do not multipost your question. It won't give you more answers. 

The 88e1111 is configured through a MDIO interface, which usually requires both hardware and software. You could probably design a state machine to configure it only through hardware only, but I don't know if it's worth the effort.
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

hai  

 

in my design also i am using marvell 88e1111. i m getting trouble with the connection establishment. while some time it is getting connected and some times it is not coming. 

can u please tell me whether it is any hardware problem or any software problem.i am driving this ic through FPGA.
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

At what level exactly? Is it the Ethernet link that isn't establishing, or a higher level connection, such as TCP? 

Does the auto-negotiation process succeed? Can you use a sniffer to see all the packets that are coming in and out? What's connected on the other side?
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

actually from my board i am connecting to the pc. it is not showing any link. when i measured clocks receive clock i am getting 25 MHz ang i am not getting TX clk actually they mentioned that it should be either 2.5 MHz or 25 or 125 MHz but m not getting these clocks i am getting 500Hz signal only. when i red the data sheet they are telling that register setting where i have to change the register setting for this TX clk through hardware can u please tell me

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

You shouldn't get 500Hz. How are you measuring it? It looks like a bad connection to me. 

Is the PHY chip answering on the MDIO pins?
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

Hi Mr.Daixiwen, 

 

actually i am measuring all the clocks belongs to the Marvell 88E1111 IC. according to the datasheet they have given that RX_CLK, TX_Clk are 2.5 MHz, 25MHZ. but for the TX_CLK i am not getting either 2.5KHz nor 25 MHz. As i measured at the MDIO pins there i am getting pulses with 4KHz. and i measured the reset pin and got correct only for reset pin. as of i tested this board 1 week before that time i didn't get any problem, that time connection establishment happen and pinging also done. now only i am getting this problem that when i am connecting to the PC it is not showing connection. can u please help me out what is the main problem for this and how to rectify this one. 

 

Thank You, 

Mamta
0 Kudos
Altera_Forum
Honored Contributor II
581 Views

Does the PHY chip answer on the MDIO pins? Is it correctly identified by the embedded software?

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

have a project a some code that many people writing at www.alterawiki.com

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

Unless you have an answer to the specific problem mentioned in the original post, it is really no use just pointing to the wiki. This isn't helping.

0 Kudos
Altera_Forum
Honored Contributor II
581 Views

still not related to the original problem

0 Kudos
Reply