TSE on Arria10 and marvell88e1512

[MatC]

Hi ,

I'm developing a custom board using the Arria10AX057H4F34E3SG.

In the FPGA I have instantiated a NIOS II processor with a TSE peripheral. The TSE is connected in SGMI mode to an external PHY MARVELL88e1512 as Ethernet PHY.

I have done a Freertos port on the NIOS II to manage the Ethernet interface. Everything seems to be working fine, i.e. the NIOS is able to send and receive packets from TSE, but something strange happens. I'm trying to send Ethernet packets to my PC and monitor the Ethernet traffic using Wireshark. When Wireshark is enabled, I'm able to see the ARP or ICMP packet sent and received by NIOS and my PC is also able to ping the NIOS device, no malformed packets are highlighted by Wireshark. When I stop the Wireshark capture, my PC stops pinging the NIOS. I've also tried to make some test with other Ethernet interface of my PC but the behaviour is the same, with some interface even if Wireshark is active I'm not able to ping the NIOS. I think that when Wireshark is active it probably disable such packet filter for this reason the PC is able to receive packet from NIOS but at the same time no errors in the packet are highlighted by Wireshark. Another strange thing I noticed is the following, the shortest packet sent from the TSE is 56 bytes long instead of canonical 60 bytes as it is visible in the attached pictures.

I tested the same software on the Arria 10 evaluation board and everything worked fine there, the only difference is the PHY model, the Arria 10 evaluation board uses a MARVELL88E1111 which is EOL.

This problem is making me crazy. I hope in your help, is there anyone who can help me?

Thanks in advance

Mat

FPGA 

[Jeet14]

Hi,

Have you also tried the same design with the MicroC/OS-II with simple socket server template on you custom board?

Example Refence link is given below-

https://www.intel.com/content/www/us/en/design-example/714912/intel-arria-10-fpga-nios-ii-processor-simple-socket-server-design-example.html

Regards

Tiwari

[MatC]

Thanks for the replay.

I'm using quartus 22.4 and the suggested example is no longer supported.
To test the example on my board I had to use Quartus 18.0 and it works fine.
At this point I have also tested my firmware with Quartus 18.0 and it works fine. One of the biggest differences I noticed is the packet length, for example the TSE in Quartus 22.4 does not pad the packet correctly, in fact the shortest packet I can see in Wireshark is 56 bytes long, the same packet sent with TSE 18.0 is 60 bytes long, in general to get the right packet length I have to add +4 to the packet length. At this point I have a question: Is there a different configuration I need to consider when configuring the newer TSE version?

Thanks in advance

[Jeet14]

Hi,

Apologies for delay as there was systems IT issues.

Please refer the below link for the preamble information.

https://www.intel.com/content/www/us/en/support/programmable/articles/000083600.html

Regards

Tiwari

[MatC]

Hi, thank you very much for the support.

Finally i found the problem, it was in the configuration of ff_tx_crc_fwd, i dont know why, but the same project compiled with Quartus 18.0 and left the ff_tx_crc_fwd input unconnected it worked fine instead with Quartus 22.4 i had to connect ff_tx_crc_fwd to logical level '0' to make the project work properly. Now the packets have the right length and I'm able to ping my board from the PC

[Jeet14]

Hi,

Glad to know this issue is resolved now.

I will close this case now but it will be open for community forum/users to respond.

Regards

Tiwari