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U-boot on NIOS II in SDRAM


I'm quite new to NIOS II and to this board - Hello everybody!

I did a small NIOS Setup with Qsys (Platform Designer)

- Clock
- NIOS 2
- some on-chip memory
...and some "Hello World" examples. It worked out and I could read my "Hello World" outputs on the nios2-terminal.

Now, I'd like to bring U-boot running onto my minimal SDRAM based NIOS Setup. Is this possible?

I neither have flash memory, nor do I want to use any of the HPS Features (such as ethernet connection or UART of my DE1 SoC). I'd like to have U-boot running, and at least show some "Hello" kind of message. Ideally I'd like to use the U-boot shell via JTAG UART (connected via USB Blaster II/USB).

So Far I figured out:

- BSP, Kernel and U-Boot can be build with Buildroot, which also provides me with a Code Sourcery SDK

- Following the U-Boot Documentation I've made a setup derrived from the 10m50 NIOS Example (generated dts from sopcinfo via java tool, board header, u-boot config). I can build U-boot with the SDK



1.) Do I need also an SPL? How does the Boot via JTAG work exactly (Document?)

2.) How do I flash my U-Boot to my NIOS 2? Can this be done via nios2-download tool?

3.) What exactly would I need to flash to the NIOS (e.g. U-boot.bin, U-boot with dts, or also with spl)?

4.) Do I need a special format of the U-boot to be able to run it in SDRAM "directly"? I saw, generally one can build a .cpio for ramfs. I'm a bit confused here, how to proceed.


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4 Replies

Hi, Lothar

May I know which FPGA you are using ? and where do you store your application code ?



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Hi Eric, thank you for trying to help me!

TL;DR: I'm still stuck in not finding the entry for u-boot's initial arch/nios/cpu/start.s code to jump in.

My specs:
SoC FPGA: Cyclone V 5CSEMA5F31C6N
Board: DE1 Rev D
IDE: Quartus 18.1 on Linux (Debian 10)

Meanwhile, I found several documents, most important I studied the "Nios II Processor Booting from Altera Serial Flash (EPCQ)" doc. I'm still trying to get U-Boot running on the before mentioned Nios II Setup (slightly modified). Trying to boot into u-boot's start.S, I understand that I'm about to implement the scenario: "Nios II processor application executes in place from EPCQ flash".

My Setup:
I added a "Serial Flash Controller II Intel FPGA IP" and named it "EPCQ". I configured it as "EPCQ256" according to the DE1 Board reference paper, I/O Mode "STANDARD".

As described in the same document, I connect "reset" and "debug_reset_request" to "reset" of the EPCQ. "data_master" and "instruction_master" go to "avl_mem" of the EPCQ. Only "data_master" connects to "avl_csr" of the EPCQ.

avl_mem shows a Base at 0x0600_0000 and IRQ 0, after executing the tcl scripts "Assign Base Addresses" and "Assign IRQs".

Memory Map in QSYS
sdram.s1 0x0000_0000 - 0x03ff_ffff
epcq.avl_mem 0x0600_0000 - 0x07ff_ffff 0x0600_0000 - 0x07ff_ffff
sram.s1 0x0800_0000 - 0x0803_ffff
nios2.debug_mem_slave 0x0804_0800 - 0x0804_0fff 0x0804_0800 - 0x0804_0fff
epcq.avl_csr 0x0804_1000 - 0x0804_103f
led.s1 0x0804_1040 - 0x0804_104f
sw.s1 0x0804_1050 - 0x0804_105f
jtag_uart.avalon_jtag_slave 0x0804_1060 - 0x0804_1067

NB: sram - I call my on-chip memory sram

In my Nios II IP, on the "vector" menu tab I set reset vector to EPCQ.avl_mem. I entered the "Reset Vector Offset" to 0x00080000. I calculate the following:

minimum reset vector offset = .sof image start adddress + .sof image size) = 0x0 + 0x00080000 = 0x00080000

My resulting reset vector then becomes 0x06080000.

size = 0x00080000 - I went by the same document's example and did a mere guess! At smaller sizes QSYS showed overlapping errors, larger sizes gave "too large" errors.

I saved everything, generated QSYS and built my setup in Quartus. I opened a shell went to the Quartus project directory and there executed
$ java -jar ./sopc2dts.jar --force-altr -i ./linux_hw.sopcinfo -o linux_hw.dts. I copied the .dts file into the u-boot sources and registered it under menuconfig. My menuconfig .config was based on the cyclone IV example of the 10m50 board in u-boot.

In the meanwhile I programmed the DE1 board using the quartus programmer. I did neither specifically add a EPCQ device in the quartus programmer, nor generate a .jic nor a .hex for that. I guess u-boot should be able to deal with all that internally.

In the u-boot sources, then I edited the include/configs/linux_hw.h, adjustments I did:
// epcq
#define CONFIG_SYS_SDRAM_BASE 0xc6000000
#define CONFIG_SYS_SDRAM_SIZE 0x02000000

#define CONFIG_SYS_MONITOR_LEN 0x00080000


Here I thought of using the 0x06080000 or 0xc6080000 as reset / start point for CONFIG_SYS_MONITOR_BASE. U-boot does some computation which leads to a adress which for sure does not work out (am I doing something wrong?). In all cases "validation failed" at some addresses. I tried several addresses, all with and without |0xc0000000.

$ nios2-download -g u-boot
Using cable "DE-SoC [1-4.2.1]", device 2, instance 0x00
Processor is already paused
Initializing CPU cache (if present)
Downloaded 263KB in 0.9s (292.2KB/s)
Verifying C6000000 ( 0%)
Verify failed between address 0xC6000000 and 0xC600FFFF
Leaving target processor paused

In another shell I left the nios2-terminal running, without any reaction.


Screening through the addresses, finally verification worked out - or at least it seemed to - at all adresses between 0xc8000000 and 0xc8040fff. Why??!!

I may nios2-elf-objcopy the u-boot to a u-boot.srec and run nios2-gdb-server on it. Bt shows me the "start()", any "step", "next" or "continue" does not show anything further. Interesting, at 0xc8040fff in particular some of my leds light up, nios2-terminal prints '4', but that's it.

Why this address? Is this really a progress, or just a weird coincidence. How to get the correct address of the RESET to jump in? Or what do I need to provide at U-boot's CONFIG_SYS_MONITOR_BASE exactly for booting into a nios 2?

Why or what do I anyway have to set here? Ain't the addresses actually already known by the DTS? Is this just a layout for how to use the SDRAM? So, but why do I need to figure out a specific RESET address? I'm confused.



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Hello Eric,


Unfortunately still not running. Sorry for the late response, I first needed to finish certain tests up to get a better idea. was one of my first place, I started actually with the instructions for the 10m50 Setup. Now after having read some more Intel documentation, re-reading rocketboards instructions gave me some new inspiration, though. Interesting, thank you! Anyway the 10m50/Cyclone IV FPGA Board differs quite a bit from my DE1SoC/Cyclone V SoC FPGA board. Another issue with approaches - aside being often a bit outdated - sometimes they seem to explain things based rather on pre-compiled binaries, attached binaries, etc. and thus often still need additional time to "reverse engineer" what the author actually tried at that time and so on. But for sure, there is still a lot of information, so I browsed BTW where did alterawiki go? Is there still a backup online?

I understood now, I'm trying the ECPQ256 in-flash boot approach. By the above mentioned article 'NIOS II Processor Booting From Altera Serial Flash (EPCQ)'. I managed to set up a .jic file, which may flash the FPGA and EPCQ flash chip persistently. A Hello Demo (compiled against "Altera HAL" functions, e.g. alt_load) came up on the setup as a verification.

In Quartus I used "Convert Programming Files" and I setup a .jic file

  • Device: cyclone V / 5CSEMA
  • The .sop: my built sop file, setting properties to "Start" instead of "Block", and having the .sop file "Compressed"
  • The .hex: I added the generated epcq.hex, I tried to leave it out and flash it manually with the shell tools later
  • This all will be bundled in a .jic file and passed persistently with the Quartus programmer onto the board (FPGA+EPCQ256 chip)

I set up the EPCQ256 Flash (4AS) and could flash it persistently. This also needs "Active Serial" to be enabled under the "Assignments" -> "Devices". After programming the board, and a power off/on or RESET, it comes up with the flashed system (which I identify by some LED settings I added).


One of my biggest issues then was how to flash binaries, respectively the u-boot ELF binary compiled for my NIOS setup? So, there is "nios2-download", there is "quartus_pgm --nios2", there is "nios2-flash-programmer", etc, etc. Same story with conversion from e.g. u-boot in .elf to .hex or to .flash. Which tool should I take? Which format is needed? Anyway am I doing the right thing anyway?


I figured out in Quartus' NIOS 2 Eclipse IDE, under "Tools" (or CTRL+7) there is a "BSP Generator" for selection of the alt_load() functions (boot ROM), and a "Flash Programmer". This tool can be set up, and will show the commands to convert and flash an ELF file. Currently first I run a conversion of the u-boot (I hope its the file with DTB included):

$ elf2flash --input=u-boot --boot=/opt/intelFPGA/18.1std/ip/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec --base=0xca000000 --end=0xcbffffff --reset=0xca080000 --verbose --output=u-boot.flash


Then I flash it via the quartus programmer or the nios2-flash-programmer, e.g.

$ quartus_pgm --nios2 --epcq --csr=0xc8081000 --base=0x0a000000 --mmu --sidp=0x0xcc081060 --debug --go u-boot.flash


As terminal application I still use nios2-terminal.

$ nios2-terminal -v


Flashing my U-boot setup to the EPCQ flash, I got a message about a missing CFI table, but I'm pretty sure about the addresses (memory map inside the "Flash Programmer"). I'll give it a try to setup a "override" file and use that for the programmer. Also with other methods (nios2-download), the nios2-terminal stays mute.

After all that I understood now, using the NIOS2 in "economy" class mode probably seems to play a role in my problem situation. I played a bit with the different NIOS2 cores in Quartus. The NIOS2 (e) does not provide great debugging features. Mainly the NIOS2 (e) does not come with an MMU thus higher virtual addresses (as in the NIOS2) templates used in u-boot) won't work. I feel I'm facing my show-stopper here. Isn't there any free license for, say, an old "classic" NIOS 2 (f) for akademic and/or no profit?

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