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hey folks,

I am new to altera stuff. I am porting my design from xilinx devices to altera devices. In that process am facing problems with DSPs porting. I am not finding dsp in altera similar to DSP48E1 to do functions like (axb) + c. I found one document Variable Precision DSP in Arria V Devices, but not finding a way to use this in Arria v. I am using Quartus II 14.0 version(trial version). I didn't even find in Ip catalog. Can some one help me on this. Thanks in advance.Link Copied

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Most designers use this hardware features by just writing behavioral code and let the design compiler choose the hardware appropriately. If you prefer structural design, look for the respective arithmetic MegaFunctions.

It's rarely required or even helpful to instantiate arithmetic hardware using low level primitives.- Mark as New
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Why cant you just do the add in the FPGA logic?

Even better, just infer the logic from HDL code. *edit* actually, you can just pass C into the LOADCONST port. http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf If you really wanted to do in inside the DSP block, you could use the 2nd multiplier input with values C and 1.- Mark as New
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hey Tricky,

Thanks for reply. But if I add outside the following problems will come. 1) it will take extra LUTs 2) it may reduce frequency as we are not sure where it will place this logic. it may take luts for routing also. Instead if I can infer directly I can use dedicated routing for dsps which may increase overall freq. As u said second solution : ( a x b + c x 1) It takes 2 dsps for multiplication, which increase overall dsps. I tried even inferring with my logic like d <= a x b; out <= d+c; In this case also also it's taking extra logic for adder. One-way If i code directly out <= (a x b) + c it's inferring as varible dsps but i want multiplier put to be registered.- Mark as New
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hey FvM,

I looked into arithmetic megafuctions. I found ALTERA_MULT_ADD, but it can do operations like a x b or (a+b) x c (it can do 4 multiplications). Preadder it can do but not (a x b) + c. Thanks.- Mark as New
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Nowadays (and has been the case for at least the last 10 years since Ive been in the industry) LUT usage is really not a problem. The bottleneck is usually the RAM or DSP usage. So using luts for an adder is really not a problem.

Also, with good pipelined design, in things like the stratix 4, acheiving 300MHz + is not a problem. So the question is - what is your target device? for easy implementation - why not go with the following code? it will infer a multiplier and an adder and should give a high fmax:```
signal a,b,c : unsigned(17 downto 0);
signal mult_out : unsigned(35 downto 0);
signal out : unsigned(36 downto 0);
process(clk)
begin
if rising_edge(clk) then
mult_out <= a * b;
out <= mult_out + c;
end if;
end process;
```

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Hey Tricky,

You are right, now days every device has many luts. it's not a problem to use luts for adder.But module which m porting is instantiated some 70 times, in that if i take 50 luts for this module(adder logic outside) it will results in 3500 luts approximately.which is a huge number. so to avoid this, m trying to infer dsp so that my design will be optimized. I am targeting arria v devicce. I implemented same way in verilog and synthesized in Quartus II 14.0 (trial version). But it's inferring adder with extra logic only. Thanks.- Mark as New
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--- Quote Start --- Hey Tricky, You are right, now days every device has many luts. it's not a problem to use luts for adder.But module which m porting is instantiated some 70 times, in that if i take 50 luts for this module(adder logic outside) it will results in 3500 luts approximately.which is a huge number. so to avoid this, m trying to infer dsp so that my design will be optimized. I am targeting arria v devicce. I implemented same way in verilog and synthesized in Quartus II 14.0 (trial version). But it's inferring adder with extra logic only. Thanks. --- Quote End --- xilinx has that sort of dsp blocks but altera doesn't though some blocks contain adders such as those for complex mult. try set your multilipcation as axb + cx1 to use them if available in your device

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Hey Tricky,

yeah, xilinix has DSP48E1 whcich can do complex operations like (a x b) + c. Altera say they have this kind of dsp ( Variable Precision DSP in Arria V Devices ). http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf. But don't know how to use them / infer them. I can do (a x b) + (c x 1) but which takes 2 dsps. Than 2 dsps going for luts is best option i think. Thanks.- Mark as New
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hey tricky,

Thanks. yeah as u said xilinx has DSP48e1 to do all complex functions. But altera also as similar primitive http://www.altera.co.uk/literature/hb/arria-v/av_52003.pdf which can do similar operations ( Variable Precision DSP in Arria V Devices). But don't know how to use it / infer it. If i use (a x b) + (c x 1) it takes 2 dsps. than 2dsps extra luts are better i think.- Mark as New
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I gave you the code to infer them already.

I suggest reading the VHDL coding guidelines for inference. http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf- Mark as New
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--- Quote Start --- I gave you the code to infer them already. I suggest reading the VHDL coding guidelines for inference. http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf --- Quote End --- hey, Thanks for info.. I synthesized following code which I found in the above document. It's inferring dsp and 17 luts for adder, 39 registers. Actually it should infer adder also inside dsp. module unsig_altmult_accum (dataout, dataa, datab, clk, aclr, clken); input [7:0] dataa, datab; input clk, aclr, clken; output reg[16:0] dataout; reg [7:0] dataa_reg, datab_reg; reg [15:0] multa_reg; wire [15:0] multa; wire [16:0] adder_out; assign multa = dataa_reg * datab_reg; assign adder_out = multa_reg + dataout; always @ (posedge clk or posedge aclr) begin if (aclr) begin dataa_reg <= 8'b0; datab_reg <= 8'b0; multa_reg <= 16'b0; dataout <= 17'b0; end else if (clken) begin dataa_reg <= dataa; datab_reg <= datab; multa_reg <= multa; dataout <= adder_out; end end endmodule

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--- Quote Start --- hey, Thanks for info.. I synthesized following code which I found in the above document. It's inferring dsp and 17 luts for adder, 39 registers. Actually it should infer adder also inside dsp. --- Quote End --- No it wont. Like we said, the DSPs only have pre-multiplier adders. So you need to do any adition before the multiply to even hope that the adder goes in the DSP.

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Finally I found solution. If we don't register multiplier output, it infers adder also into dsp.

with the following code. wire [35:0] mul_out = ((mul_a_in[17:0]) * (mul_b_in[17:0])); assign adder_out = $signed(add_c_in[35:0] + mul_out); it can do (36 bit + (18 x 18)).- Mark as New
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but unless you register the adder output, you're going to get poorer fmax.

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--- Quote Start --- but unless you register the adder output, you're going to get poorer fmax. --- Quote End --- hey tricky, That registering can be done in dsp itself, Even we can register inputs also once inside dsp. this is the dsp inside arria v. http://www.alteraforum.com/forum/attachment.php?attachmentid=9723&stc=1 This is the dsp inside arria V series devices.

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