I have designwed a custom UART (tested with timinmg simulation and with Signal Tap - working as expected) with 16byte FIFO in Rx and Tx section.
This I am including as peripheral in Nios II system through new component wizard.
The data from RxFIFO is available on the readdata lines of UART 1.5 clock after
read for FIFO is asserted. i.e 1 clock latency.
In the New component wizard I have specified Read wait as 0 cycles and read latency as 1. Noe the UART receives the data properly when single caracter is transmitted from other UART but if multiple characters are transfered say A B C D E then it prints every chararcter multiple times successively i.e. A A A A A B B B etc.
Its transmitting properly with write wait state of 0.
If the UARt tested independent of the Nios system functions properly whhats going wrong when included as peripheral in the system.
Any help!!
Reagrds
