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What is the on chip ram (FPGA) requirement for nios II execute in place with QSPI


I am thinking about doing an execute in place architecture using a QSPI device with a NIOSII embedded in a Cyclone 10LP. I am doing this to reduce the amount of on chip ram used inside the FPGA. However, from what I understand, this architecture still requires on chip ram to hold things like the 'Stack' and 'heap' etc... i.e. the writable parts of the application code memory.


If anyone has done this, might they be able to tell me roughly how many M9K blocks (or memory bits) they used of the FPGA's on chip ram. My design is not anything major.



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the RAM in general is required by Nios II to execute even if you select XIP flash option. There is still a need to write data, which is not possible on flash to implement.

If you want to reduce the RAM size used by your application, I would recommend to start with hello_world_small template. The RAM size needed for Nios II application is subjective, ranged from 8Kb to infinity.

You might try to start with 16Kb and see if you can compile your application. From the compilation report, you can check the size of your executable code with the remaining space. Please note that you need to keep some empty space for stack/heap operations.


Thank you.


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