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about DCLK frequency of EPM7128

Altera_Forum
Honored Contributor II
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hello everyone 

 

config_controller.tdf :  

 

NOTE: DCLK = ~3.125MHz 

-- This particular design is set up for a 50MHz input clock frequency. You  

-- can set it up for any input clock frequency you want by changing the 

-- "dclk_divider" preload value. 

 

Who can tell me how to determine the DCLK frequence of EPM7128 that has connected to stratix EP1s25 , the input oscillator frequence is : 80M. 

 

 

thank you!
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Altera_Forum
Honored Contributor II
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Hello ffone13, 

 

DLCK is the clock for the serial configuration of the FPGA. The maximum value is given in the datasheet of your FPGA. The config controller is using the dclk_divider to generate the data clock (DLCK) out of the input clock. 

 

Bye, 

niosIIuser
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